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31. 发明申请

US20100306568A1 SYMMETRICAL CLOCK DISTRIBUTION IN MULTI-STAGE HIGH SPEED DATA CONVERSION CIRCUITS 有权
标题翻译：多级高速数据转换电路中的对称时钟分配
公开(公告)号：US20100306568A1
公开(公告)日：2010-12-02
申请号：US12857049
申请日：2010-08-16
申请人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
发明人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
IPC分类号： G06F1/04
CPC分类号： H04J3/0685 , H04J3/04 , H04J3/0629 , H04L7/0008
摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).
摘要翻译：提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。时钟分配电路接收并对称地将时钟信号分配给数据转换电路。耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

32. 发明申请

US20100025263A1 NANOPORE PARTICLE ANALYZER, METHOD OF PREPARATION AND USE THEREOF 审中-公开
标题翻译：纳米粒子分析仪，其制备方法和用途
公开(公告)号：US20100025263A1
公开(公告)日：2010-02-04
申请号：US11743536
申请日：2007-05-02
申请人： Henry S. White , Bo Zhang , Ryan J. White , Eric N. Ervin
发明人： Henry S. White , Bo Zhang , Ryan J. White , Eric N. Ervin
IPC分类号： C12Q1/06 , G01N27/28 , G01N27/26 , B23P11/00
CPC分类号： G01N33/48721 , B82Y15/00 , G01N15/12 , Y10T29/49826
摘要： Provided are the preparation, characterization, and application of a nanopore membrane device. The nanopore device comprises a thin membrane prepared from glass, fused silica, ceramics or quartz, containing one or more nanopores ranging from about 2 nm to about 500 nm. The nanopore is prepared by a template method using sharpened metal wires and the size of the pore opening can be controlled during fabrication by an electrical feedback circuit. The nanopore device is particularly useful for counting and analyzing nanoparticles of radius less than 400 nm.
摘要翻译：提供纳米孔膜装置的制备，表征和应用。纳米孔装置包括由玻璃，熔融石英，陶瓷或石英制备的薄膜，其含有一个或多个范围为约2nm至约500nm的纳米孔。通过使用尖锐金属线的模板法制备纳米孔，并且可以通过电反馈电路在制造期间控制孔隙的尺寸。纳米孔装置对于计数和分析半径小于400nm的纳米粒子是特别有用的。

33. 发明申请

US20090285405A1 METHOD FOR MANUFACTURING ARRAY MICROPHONES AND SYSTEM FOR CATEGORIZING MICROPHONES 有权
标题翻译：制造阵列微阵列的方法和用于分类麦克风的系统
公开(公告)号：US20090285405A1
公开(公告)日：2009-11-19
申请号：US12121066
申请日：2008-05-15
申请人： Bo Zhang , Lili Chen , Jie Yu
发明人： Bo Zhang , Lili Chen , Jie Yu
IPC分类号： H04R29/00
CPC分类号： H04R29/00 , H04R2201/403
摘要： The invention provides a method for manufacturing array microphones. First, signal delays of a plurality of microphones are measured. The microphones are then categorized into a plurality of categories according to the signal delays. A plurality of array microphones are then assembled with a number of component microphones selected from the same categories.
摘要翻译：本发明提供一种制造阵列麦克风的方法。首先，测量多个麦克风的信号延迟。然后，麦克风根据信号延迟被分类成多个类别。然后将多个阵列麦克风与从相同类别中选择的多个组件麦克风组装。

34. 发明申请

US20090108673A1 METHOD FOR DETERMINING A VOLTAGE LEVEL ACROSS AN ELECTRIC CIRCUIT OF A POWERTRAIN 有权
标题翻译：用于确定动力系统的电路中的电压电平的方法
公开(公告)号：US20090108673A1
公开(公告)日：2009-04-30
申请号：US12253214
申请日：2008-10-16
申请人： Wei D. Wang , William R. Cawthorne , Aniket Kothari , Nicolas Kokotovich , Wei Ren , Bo Zhang
发明人： Wei D. Wang , William R. Cawthorne , Aniket Kothari , Nicolas Kokotovich , Wei Ren , Bo Zhang
IPC分类号： G01R19/00 , B60L1/00
CPC分类号： B60W20/00 , B60K1/02 , B60K6/365 , B60K6/445 , B60K6/547 , B60L3/0046 , B60L11/123 , B60L11/14 , B60L11/1851 , B60L11/187 , B60L2240/423 , B60L2240/441 , B60L2240/443 , B60L2240/445 , B60L2240/461 , B60L2240/465 , B60L2240/486 , B60L2240/662 , B60W10/02 , B60W10/06 , B60W10/08 , B60W2510/0638 , B60W2510/0657 , B60W2510/0671 , B60W2510/0676 , B60W2510/1015 , B60W2510/104 , B60W2510/244 , B60W2510/246 , B60W2520/28 , B60W2540/10 , B60W2540/12 , B60W2540/16 , B60W2550/12 , B60W2710/027 , B60W2710/0605 , B60W2710/0616 , B60W2710/0666 , B60W2710/083 , Y02T10/6217 , Y02T10/6239 , Y02T10/6286 , Y02T10/642 , Y02T10/7005 , Y02T10/705 , Y02T10/7077 , Y02T10/7291 , Y02T90/16
摘要： A method for determining a voltage level across an electrical circuit of a powertrain includes measuring a plurality of voltage levels and utilizing a comparison test between at least two voltage levels of the plurality of voltage levels to determine the circuit voltage level.
摘要翻译：用于确定跨越动力系的电路的电压电平的方法包括测量多个电压电平并且利用多个电压电平的至少两个电压电平之间的比较测试来确定电路电压电平。

35. 外观设计

USD582633S1 Pocket 有权
标题翻译：口袋
公开(公告)号：USD582633S1
公开(公告)日：2008-12-16
申请号：US29308554
申请日：2008-06-20
申请人： Bo Zhang
设计人： Bo Zhang

36. 发明申请

US20080121534A1 NANOPORE ELECTRODE, NANOPORE MEMBRANE, METHODS OF PREPARATION AND SURFACE MODIFICATION, AND USE THEREOF 有权
标题翻译： NANOPORE ELECTRODE，NANOPORE MEMBRANE，METHODS OF PROBARATION AND SURFACE MODIFICATION，AND USE THEREOF
公开(公告)号：US20080121534A1
公开(公告)日：2008-05-29
申请号：US11744154
申请日：2007-05-03
申请人： Henry S. White , Bo Zhang , Ryan J. White , Eric N. Ervin , Gangli Wang
发明人： Henry S. White , Bo Zhang , Ryan J. White , Eric N. Ervin , Gangli Wang
IPC分类号： G01N27/26 , B32B38/10 , C23F1/00
CPC分类号： B01D71/04 , B01D67/006 , B01D2325/021 , Y10S977/904 , Y10S977/953 , Y10T29/49 , Y10T29/49002 , Y10T29/49004 , Y10T29/49826
摘要： Provided are fabrication, characterization and application of a nanodisk electrode, a nanopore electrode and a nanopore membrane. These three nanostructures share common fabrication steps. In one embodiment, the fabrication of a disk electrode involves sealing a sharpened internal signal transduction element (“ISTE”) into a substrate, followed by polishing of the substrate until a nanometer-sized disk of the ISTE is exposed. The fabrication of a nanopore electrode is accomplished by etching the nanodisk electrode to create a pore in the substrate, with the remaining ISTE comprising the pore base. Complete removal of the ISTE yields a nanopore membrane, in which a conical shaped pore is embedded in a thin membrane of the substrate.
摘要翻译：提供了纳米棒电极，纳米孔电极和纳米孔膜的制造，表征和应用。这三种纳米结构具有共同的制造步骤。在一个实施例中，盘形电极的制造包括将锐化的内部信号转导元件（“ISTE”）密封到衬底中，随后抛光衬底直至暴露出ISTE的纳米尺寸的盘。纳米孔电极的制造通过蚀刻纳米盘电极以在衬底中产生孔而实现，剩余的ISTE包含孔基。完全去除ISTE产生纳米孔膜，其中锥形孔被嵌入在基底的薄膜中。

37. 发明申请

US20070075397A1 On-chip capacitor structure 有权
标题翻译：片上电容器结构
公开(公告)号：US20070075397A1
公开(公告)日：2007-04-05
申请号：US11241142
申请日：2005-09-30
申请人： Bo Zhang
发明人： Bo Zhang
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L27/0805 , H01L28/87 , H01L28/91 , H01L29/93 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and a second capacitor is formed on the substrate and connected to a second differential node of the differential circuit. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate.
摘要翻译：第一电容器形成在衬底上并连接到差分电路的第一差分节点，并且第二电容器形成在衬底上并连接到差分电路的第二差分节点。第三电容器连接在第一差分节点和第二差分节点之间，并且至少部分地形成在第一电容器的上方。以这种方式，可以在基板上减小第一电容器和/或第二电容器的尺寸。

38. 发明申请

US20060222251A1 Method and system for frame/field coding 审中-公开
标题翻译：帧/场编码的方法和系统
公开(公告)号：US20060222251A1
公开(公告)日：2006-10-05
申请号：US11096468
申请日：2005-04-01
申请人： Bo Zhang
发明人： Bo Zhang
IPC分类号： G06K9/36
CPC分类号： H04N19/533 , H04N19/112 , H04N19/16
摘要： Described herein is a system and method for encoding video data with motion estimation. The system and method can optimize memory usage and enhance the perceptual quality of an encoded picture by combining the processes in adaptive frame/field coding.
摘要翻译：这里描述了一种用于利用运动估计对视频数据进行编码的系统和方法。该系统和方法可以通过组合自适应帧/场编码中的处理来优化存储器使用并增强编码图像的感知质量。

39. 发明申请

US20060222063A1 Method and system for rate control in a video encoder 失效
标题翻译：视频编码器速率控制方法及系统
公开(公告)号：US20060222063A1
公开(公告)日：2006-10-05
申请号：US11096467
申请日：2005-04-01
申请人： Bo Zhang , Reinhard Schumann
发明人： Bo Zhang , Reinhard Schumann
IPC分类号： H04N11/04 , H04N7/12 , H04B1/66 , H04N11/02
CPC分类号： H04N19/53 , H04N19/102 , H04N19/103 , H04N19/124 , H04N19/146 , H04N19/172 , H04N19/176 , H04N19/177 , H04N19/56 , H04N19/91
摘要： Described herein is a rate controller in a video system. The rate controller estimates a bit count, and controls three adaptive rate control loops. The master rate control loop is in control of the quantizer. The slave rate control loops control coarse motion estimation and fine motion estimation.
摘要翻译：这里描述的是视频系统中的速率控制器。速率控制器估计位计数，并控制三个自适应速率控制回路。主速率控制回路控制量化器。从速率控制循环控制粗略运动估计和精细运动估计。

40. 发明申请

US20060002497A1 PHASE ADJUSTMENT METHOD AND CIRCUIT FOR DLL-BASED SERIAL DATA LINK TRANSCEIVERS 失效
标题翻译：基于DLL的串行数据链路收发器的相位调整方法和电路
公开(公告)号：US20060002497A1
公开(公告)日：2006-01-05
申请号：US10882428
申请日：2004-07-02
申请人： Bo Zhang
发明人： Bo Zhang
IPC分类号： H04B17/00 , H03D1/00 , H04L27/06 , H04L7/00
CPC分类号： H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/033 , H04L7/0337 , H04L27/06
摘要： A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal. The phase control signal can be a digital signal comprising a plurality of bits corresponding to a phase relationship between the 0° clock and 180° clock. The timing recovery circuit can be a digital circuit. The phase control signal is used to maintain a transition of the 0° clock near a center of an “eye” in the input data.
摘要翻译：一个延迟锁定环电路，具有由0°时钟驱动并接收输入数据的第一触发器。一个180°时钟的第二个触发器，并接收输入数据。第一解复用器接收第一触发器的输出并输出峰值数据。第二解复用器接收第二触发器的输出并输出零数据。定时恢复电路根据零数据和峰值数据输出相位控制位。第一相位内插器基于相位控制信号输出0°时钟。第二相位内插器根据相位控制信号输出180°时钟。相位寄存器从定时恢复电路接收相位控制信号。第一和第二触发器可以是D触发器。第一和第二相位内插器根据相位控制信号调节0°时钟和180°时钟的相对相位。相位控制信号可以是包括对应于0°时钟和180°时钟之间的相位关系的多个位的数字信号。定时恢复电路可以是数字电路。相位控制信号用于保持输入数据中靠近“眼睛”中心的0°时钟的转变。

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