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31. 发明授权

US08891854B2 Device and method for transforming 2D images into 3D images 有权
标题翻译：将2D图像转换为3D图像的设备和方法
公开(公告)号：US08891854B2
公开(公告)日：2014-11-18
申请号：US13435238
申请日：2012-03-30
申请人： Chun-Hsing Hsieh , Hsu-Jung Tung , Chia-Wei Yu
发明人： Chun-Hsing Hsieh , Hsu-Jung Tung , Chia-Wei Yu
IPC分类号： G06K9/00 , H04N13/02 , H04N13/04
CPC分类号： H04N13/261 , H04N13/341
摘要： A device for transforming 2D images into 3D images includes a position calculation unit and an image processing block. The position calculation unit generates multiple start points corresponding to multiple pixel lines of a panel according to a display type of the panel. The image processing block reshapes multiple input enable signals into multiple output enable signals according to the start points. The pixel lines of the panel displays the output data signal as multiple image signals respectively according to the output enable signals. The image signals include multiple left-eye image signals and multiple right-eye image signals.
摘要翻译：用于将2D图像变换为3D图像的装置包括位置计算单元和图像处理块。位置计算单元根据面板的显示类型生成与面板的多个像素线对应的多个起始点。图像处理块根据起始点将多个输入使能信号重新形成多个输出使能信号。面板的像素线根据输出使能信号分别显示输出数据信号作为多个图像信号。图像信号包括多个左眼图像信号和多个右眼图像信号。

32. 发明授权

US08868827B2 FIFO apparatus for the boundary of clock trees and method thereof 有权
标题翻译：时钟树边界的FIFO设备及其方法
公开(公告)号：US08868827B2
公开(公告)日：2014-10-21
申请号：US13418882
申请日：2012-03-13
申请人： Hsu-Jung Tung , Sen-Huang Tang
发明人： Hsu-Jung Tung , Sen-Huang Tang
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00 , G06F5/06 , G06F1/04
CPC分类号： G06F5/06 , G06F1/04 , G06F5/10
摘要： A FIFO apparatus uses a first clock signal in a first clock domain to receive an input signal and uses a second clock signal in a second clock domain to output an output signal. An example apparatus includes: at least three write registers belonging to the first clock domain for receiving the input signal. Each of the write registers has a first output. A first controller belonging to the first clock domain enables the registers, in accordance with an order, to generate an initial signal. A multiplexer receives the first outputs. A second controller belonging to the second clock domain, receives the initial signal through an asynchronous interface and controls the multiplexer to output the first outputs in accordance with the order to be the output signal, wherein the second clock domain is a clock tree generated based on the first clock domain.
摘要翻译： FIFO装置使用第一时钟域中的第一时钟信号来接收输入信号，并且在第二时钟域中使用第二时钟信号来输出输出信号。示例性装置包括：属于第一时钟域的至少三个写入寄存器，用于接收输入信号。每个写入寄存器都有一个第一个输出。属于第一时钟域的第一控制器使得寄存器能够根据命令产生初始信号。多路复用器接收第一输出。属于第二时钟域的第二控制器通过异步接口接收初始信号，并控制多路复用器根据顺序将第一输出输出为输出信号，其中第二时钟域是基于第一个时钟域。

33. 发明申请

US20070201475A1 PACKET PROCESSING SYSTEM AND RELATED PACKET PROCESSING METHOD 审中-公开
标题翻译：分组处理系统及相关分组处理方法
公开(公告)号：US20070201475A1
公开(公告)日：2007-08-30
申请号：US11674154
申请日：2007-02-13
申请人： Kuo-Yang Li , Tzuo-bo Lin , Hsu-Jung Tung
发明人： Kuo-Yang Li , Tzuo-bo Lin , Hsu-Jung Tung
IPC分类号： H04L12/56
CPC分类号： H04N5/775 , H04L69/12 , H04N21/2389 , H04N21/4385 , H04N21/6332 , H04N21/654
摘要： A packet processing system includes: a receiver for receiving a previous packet and a current packet through an interface; a storage device for storing the previous packet; a comparing module, coupled to the storage device and the receiver, for comparing contents of the current packet with contents of the previous packet to generate a comparison result; and a packet reading module, coupled to the storage device, for reading the contents of the current packet according to the comparison result.
摘要翻译：分组处理系统包括：接收器，用于通过接口接收先前分组和当前分组; 用于存储先前分组的存储设备; 耦合到存储设备和接收器的比较模块，用于将当前分组的内容与先前分组的内容进行比较以产生比较结果; 以及分组读取模块，耦合到存储设备，用于根据比较结果读取当前分组的内容。

34. 发明申请

US20070174523A1 APPARATUS AND METHOD FOR GENERATING BITSTREAM OF S/PDIF DATA IN HDMI 有权
标题翻译：用于生成HDMI中S / PDIF数据的BITSTREAM的装置和方法
公开(公告)号：US20070174523A1
公开(公告)日：2007-07-26
申请号：US11306703
申请日：2006-01-09
申请人： Tzuo-bo Lin , Hsu-Jung Tung , Sheng-Nan Chiou , Chia-Sheng Tsai
发明人： Tzuo-bo Lin , Hsu-Jung Tung , Sheng-Nan Chiou , Chia-Sheng Tsai
IPC分类号： G06F13/38
CPC分类号： G06F13/4295
摘要： An apparatus and method for regenerating S/PDIF data is disclosed. The apparatus includes a buffer for buffering sample words of the data units; a decision unit for receiving control words of the data units and outputting a selected control word according to a current control word of a current data unit and a previous control word of a previous data unit; and a transmitter for generating the bitstream of the first digital interconnect format according to the sample words of the data units and the selected control words outputted from the decision unit.
摘要翻译：公开了一种用于再生S / PDIF数据的装置和方法。该装置包括用于缓冲数据单元的采样字的缓冲器; 决定单元，用于接收数据单元的控制字，并根据当前数据单元的当前控制字和先前数据单元的先前控制字输出所选择的控制字; 以及发送器，用于根据数据单元的采样字和从判定单元输出的所选择的控制字来产生第一数字互连格式的比特流。

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