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31. 发明授权

US08748888B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08748888B2
公开(公告)日：2014-06-10
申请号：US12648680
申请日：2009-12-29
申请人： Jeong Woo Lee , Hyung Dong Lee , Jun Gi Choi , Sang Hoon Shin , Xiang Hua Cui
发明人： Jeong Woo Lee , Hyung Dong Lee , Jun Gi Choi , Sang Hoon Shin , Xiang Hua Cui
IPC分类号： H01L23/58
CPC分类号： H01L25/0657 , G01R31/2884 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.
摘要翻译：半导体集成电路包括具有多个半导体芯片的多芯片封装。半导体集成电路包括信号线; 以及多个半导体芯片中的半导体芯片中的信号负载补偿部，被配置为响应于测试信号的激活而将设计的信号加载到信号线。这里，设计的信号负载具有与信号线的多个半导体芯片中的另一半导体芯片的信号负载分量相对应的值。

32. 发明授权

US08514641B2 Repair circuit and repair method of semiconductor apparatus 有权
标题翻译：半导体装置修理电路及修理方法
公开(公告)号：US08514641B2
公开(公告)日：2013-08-20
申请号：US12840231
申请日：2010-07-20
申请人： Xiang Hua Cui , Jeong Woo Lee , Sang Hoon Shin
发明人： Xiang Hua Cui , Jeong Woo Lee , Sang Hoon Shin
IPC分类号： G11C7/00
CPC分类号： G11C29/702
摘要： A repair circuit of a semiconductor apparatus includes a plurality of through-silicon vias including repeated sets of one repair through-silicon via and an M number of normal through-silicon vias; a transmission unit configured to multiplex input data at a first multiplexing rate based on control signals, and transmit the multiplexed data to the plurality of through-silicon vias; a reception unit configured to multiplex signals transmitted through the plurality of through-silicon vias at a second multiplexing rate based on the control signals, and generate output data; and a control signal generation unit configured to generate sets of the control signals based on an input number of a test signal.
摘要翻译：半导体装置的修复电路包括多个穿硅通孔，包括重复的一组修复通硅通孔和M个通常的硅通孔; 传输单元，被配置为基于控制信号以第一多路复用速率复用输入数据，并将多路复用数据发送到多个通孔通孔; 接收单元，被配置为基于所述控制信号以第二多路复用速率复用通过所述多个穿硅通孔传输的信号，并生成输出数据; 以及控制信号生成单元，被配置为基于测试信号的输入号码生成控制信号的集合。

33. 发明申请

US20110238900A1 Method of managing a solid state drive, associated systems and implementations 审中-公开
标题翻译：管理固态驱动器，相关系统和实现的方法
公开(公告)号：US20110238900A1
公开(公告)日：2011-09-29
申请号：US13067436
申请日：2011-06-01
申请人： Jin Gyu Heo , Donggi Lee , Seongsik Hwang , Dongjin Lee , Jeong Woo Lee , Wonmoon Cheon , Seungho Lim , Jong-Min Kim , Jae-Hwa Lee , Haeri Lee , Woonhyug Jee
发明人： Jin Gyu Heo , Donggi Lee , Seongsik Hwang , Dongjin Lee , Jeong Woo Lee , Wonmoon Cheon , Seungho Lim , Jong-Min Kim , Jae-Hwa Lee , Haeri Lee , Woonhyug Jee
IPC分类号： G06F12/02
CPC分类号： G06F9/4403 , G06F9/4406 , G06F12/0246 , G06F13/1673 , G06F2212/7201 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, the method includes storing, by a status checking module, status information for a solid state drive, and determining a status state of the solid state drive based on the status information. The status state is one of a good state, an intermediate state and a bad state, and the intermediate state is a state between the good state and the bad state.
摘要翻译：在一个实施例中，该方法包括由状态检查模块存储固态驱动器的状态信息，以及基于状态信息确定固态驱动器的状态。状态是好状态，中间状态和坏状态之一，中间状态是良好状态与坏状态之间的状态。

34. 发明授权

US08022374B2 Holder device for analyzing characteristics of dosimeter 有权
标题翻译：用于分析剂量计特性的持有者装置
公开(公告)号：US08022374B2
公开(公告)日：2011-09-20
申请号：US11775881
申请日：2007-07-11
申请人： Tae Suk Seo , Jin Beom Chung , Jeong Woo Lee , Yon Lae Kim , Kyoung Sik Choi , Seoung Jong Oh , Jai Woong Yoon
发明人： Tae Suk Seo , Jin Beom Chung , Jeong Woo Lee , Yon Lae Kim , Kyoung Sik Choi , Seoung Jong Oh , Jai Woong Yoon
IPC分类号： H05K5/00
CPC分类号： G01T1/02
摘要： Provided is a holder device for analyzing characteristics of a dosimeter. In the holder device, the dosimeter is located in a desired direction on a radiation path along which radiation is irradiated from a radiation emitter, and a radiation absorbance characteristic is recognized according to a radiation dose absorbed by the dosimeter. The holder device includes: a dosimeter holder fixedly supporting the dosimeter; a body having a partial spherical portion with a specific curvature, and having a plurality of mounting holes containing the dosimeter holder; and a supporter supporting the body so that the dosimeter is located on the radiation path. Accordingly, in the holder device for analyzing characteristics of a dosimeter, one or more dosimeters can be disposed at a desired angle and position with respect to a radiation emitter, characteristics of the dosimeter can be accurately analyzed, and thus radiation treatment and treatment schedule can be effectively performed.
摘要翻译：提供了一种用于分析剂量计的特性的保持装置。在保持器装置中，剂量计位于从辐射发射器照射辐射的辐射路径上的期望方向上，并且根据剂量计吸收的辐射剂量识别辐射吸收特性。支架装置包括：固定地支撑剂量计的剂量计支架; 具有具有特定曲率的部分球形部分的主体，并且具有容纳所述剂量计保持器的多个安装孔; 以及支撑身体的支撑件，使得剂量计位于辐射路径上。因此，在用于分析剂量计的特性的保持装置中，可以将一个或多个剂量计相对于辐射发射器设置在期望的角度和位置，可以准确地分析剂量计的特性，因此辐射治疗和治疗计划可以有效地执行。

35. 发明申请

US20100091599A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20100091599A1
公开(公告)日：2010-04-15
申请号：US12347055
申请日：2008-12-31
申请人： Hyung Wook Moon , Jeong Woo Lee , Won Jun Choi
发明人： Hyung Wook Moon , Jeong Woo Lee , Won Jun Choi
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1045 , G11C11/408
摘要： A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks, wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal.
摘要翻译：半导体存储装置包括第一和第二存储块，模式发生器，被配置为产生用于控制第一和第二存储块的操作模式的芯片选择模式信号;以及控制器，被配置为响应于驱动第一和第二存储块与芯片选择模式信号，第一和第二选择信号以及用于控制第一和第二存储块的驱动的预定地址信号，其中控制器接收具有用于确定单个芯片的电平的芯片选择模式信号模式，以一个等级单位来控制第一和第二存储区块的操作，并且通过使用预定的地址信号来选择性地激活第一和第二存储体块。

36. 发明授权

US07526665B2 Electrically controlled suspension system 有权
标题翻译：电控悬挂系统
公开(公告)号：US07526665B2
公开(公告)日：2009-04-28
申请号：US11347180
申请日：2006-02-03
申请人： Wan Il Kim , Jeong Woo Lee
发明人： Wan Il Kim , Jeong Woo Lee
IPC分类号： G06F1/00 , A01B69/00
CPC分类号： B60G17/08 , B60G17/015 , B60G17/0152 , B60G2400/102 , B60G2400/202 , B60G2400/82 , B60G2500/10 , B60G2800/702
摘要： An electronically controlled suspension system according to the present invention comprises a sensor unit for extracting and providing a vertical acceleration component of a vehicle body of a vehicle; a signal processing unit for calculating a vertical velocity of the vehicle body using the vertical acceleration component provided by the sensor unit; a control gain determining unit having a control gain set according to the amplitude of the vertical acceleration component, and detecting the amplitude of the vertical acceleration component provided by the sensor unit and extracting a control gain corresponding to the detected amplitude; a control command value calculating unit for calculating a control command value using the control gain provided by the control gain determining unit and the vertical velocity of the vehicle body provided by the signal processing unit; and a damper driving unit for driving the variable damper based in the control command value.According to the present invention described above, a control command value for use in controlling a damping force of a damper is calculated using a nonlinear control gain according to a signal outputted from a speed or vertical acceleration sensor, thereby securing ride comfort and control stability.
摘要翻译：根据本发明的电子控制悬架系统包括用于提取和提供车辆车身的垂直加速度分量的传感器单元; 信号处理单元，用于使用由传感器单元提供的垂直加速度分量来计算车体的垂直速度; 控制增益确定单元，具有根据所述垂直加速度分量的振幅设定的控制增益，并且检测由所述传感器单元提供的所述垂直加速度分量的幅度，并提取与所述检测到的幅度相对应的控制增益; 控制指令值计算单元，用于使用由控制增益确定单元提供的控制增益和由信号处理单元提供的车身垂直速度来计算控制命令值; 以及阻尼器驱动单元，用于基于控制命令值驱动可变阻尼器。根据上述本发明，使用根据从速度或垂直加速度传感器输出的信号的非线性控制增益来计算用于控制阻尼器的阻尼力的控制指令值，从而确保乘坐舒适性和控制稳定性。

37. 发明授权

US07482856B2 VPP voltage generator for generating stable VPP voltage 有权
标题翻译： VPP电压发生器，用于产生稳定的VPP电压
公开(公告)号：US07482856B2
公开(公告)日：2009-01-27
申请号：US11319565
申请日：2005-12-29
申请人： Jeong Woo Lee
发明人： Jeong Woo Lee
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： The present invention relates to a VPP voltage generator that generates a stable VPP voltage. The VPP voltage generator of the present invention generates a stable VPP voltage. Therefore, power consumption can be saved, a precharge time of word line can be prevented from increasing and a tRCD characteristic can be improved. It is thus possible to improve the operational performance of semiconductor memory devices.
摘要翻译：本发明涉及产生稳定的VPP电压的VPP电压发生器。本发明的VPP电压发生器产生稳定的VPP电压。因此，可以节省功耗，可以防止字线的预充电时间增加，并且可以提高tRCD特性。因此可以提高半导体存储器件的操作性能。

38. 发明授权

US07466621B2 Row address controller 有权
标题翻译：行地址控制器
公开(公告)号：US07466621B2
公开(公告)日：2008-12-16
申请号：US11683609
申请日：2007-03-08
申请人： Jeong Woo Lee
发明人： Jeong Woo Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C8/08
摘要： Disclosed is a row address controller comprising: a bank control unit generating an active pulse and a precharge pulse, a word line clear signal and a block selection enable signal using the active pulse and precharge pulse. An address decoder latches and decodes a row address signal in response to a decoder enable signal and outputs a first and second address signals. A block selection unit generates a block selection signal in response to a redundancy signal, a repair signal, the word line clear signal, the block selection signal and the first address signal. A block control unit generates a word line latch signal in response to the precharge pulse and block selection signal A latch unit latches and outputs the second address signal in response to the word line latch signal.
摘要翻译：公开了一种行地址控制器，包括：使用有源脉冲和预充电脉冲产生有效脉冲和预充电脉冲，字线清除信号和块选择使能信号的存储体控制单元。地址解码器响应于解码器使能信号来锁存和解码行地址信号，并输出第一和第二地址信号。块选择单元响应于冗余信号，修复信号，字线清除信号，块选择信号和第一地址信号产生块选择信号。块控制单元响应于预充电脉冲产生字线锁存信号，块选择信号A锁存单元锁存并响应于字线锁存信号输出第二地址信号。

39. 发明申请

US20080253277A1 OFDM receiving circuit having multiple demodulation paths using oversampling analog-to-digital converter 有权
标题翻译： OFDM接收电路具有使用过采样模数转换器的多个解调路径
公开(公告)号：US20080253277A1
公开(公告)日：2008-10-16
申请号：US11976909
申请日：2007-10-29
申请人： Seung Wook Lee , Joonbae Park , Jeong Woo Lee , Su Won Kang , Kyeongho Lee
发明人： Seung Wook Lee , Joonbae Park , Jeong Woo Lee , Su Won Kang , Kyeongho Lee
IPC分类号： H04J11/00
CPC分类号： H04L27/2647
摘要： Embodiments according to the application relates to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths for an oversampling ADC, which can increase or improve an overall performance of the circuit.
摘要翻译：根据本申请的实施例涉及一种OFDM（正交频分复用）接收电路及其方法，被配置为具有用于过采样ADC的多个解调路径，其可以增加或提高电路的整体性能。

40. 发明申请

US20080212662A1 APPARATUS FOR MEASURING IQ IMBALANCE 有权
标题翻译：测量智商不平等的方法
公开(公告)号：US20080212662A1
公开(公告)日：2008-09-04
申请号：US12027762
申请日：2008-02-07
申请人： Kyeongho Lee , Joonbae Park , Jeong Woo Lee , Seung-Wook Lee , Eal Wan Lee
发明人： Kyeongho Lee , Joonbae Park , Jeong Woo Lee , Seung-Wook Lee , Eal Wan Lee
IPC分类号： H04L25/06 , H04B17/00 , H04B3/46 , H04Q1/20
CPC分类号： H03D7/166 , H03D3/009 , H04L25/061 , H04L27/364 , H04L27/3863 , H04L2027/0016
摘要： The present general inventive concept relates to apparatuses and/or methods for measuring an IQ imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.
摘要翻译：本发明总体构思涉及用于测量IQ不平衡的装置和/或方法。在一个实施例中，信号发生器可以在第一周期期间提供DC分量的第一IQ信号，并且在第二周期期间提供第一角频率的第一IQ信号，IQ上变频混频器可以上变频第一IQ信号在第一周期期间以第二角度频率进行第二角度频率，并且在第二周期期间将第一IQ信号上升转换第三角度频率以输出第二IQ信号，IQ降频转换混频器可以将第二IQ信号下变频第三IQ信号输出第三IQ信号和IQ不平衡检测器的角频率可以在第一周期期间从第三IQ信号和第二IQ不平衡（例如，Tx / Rx IQ不平衡）获得第一IQ不平衡（例如，Rx IQ不平衡）第二期。

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