专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06212111B1 Synchronous dynamic random access memory device 有权
公开(公告)号：US06212111B1
公开(公告)日：2001-04-03
申请号：US09572390
申请日：2000-05-16
申请人： Jeffrey P. Wright , Hua Zheng
发明人： Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C700
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/109
摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

32. 发明授权

US06190972B1 Method for storing information in a semiconductor device 失效
标题翻译：用于在半导体器件中存储信息的结构和方法
公开(公告)号：US06190972B1
公开(公告)日：2001-02-20
申请号：US08946027
申请日：1997-10-07
申请人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
发明人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
IPC分类号： H01L218246
CPC分类号： G01R31/3181 , G11C17/10 , H01L27/112
摘要： A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer. Each of the storage elements is formed in a predetermined state such that they collectively store a digital value that identifies a mask used to form the conductive layer.
摘要翻译：半导体器件包括形成在衬底上的多个导电层。共同组成存储元件的只读存储元件（例如熔丝元件）的两个电互相耦合部分分别形成在不同的一个导电层中。存储元件具有存储状态，并且每个部分具有导电性。可以通过改变其中一个部分的电导率来改变存储元件的存储状态。另外，多个存储元件可以并联耦合以形成存储模块。存储模块的每个存储元件可以包括各自形成在不同导电层中的多个存储部分。存储元件可以存储用于形成半导体器件的掩模集的版本号。或者，在衬底上形成导电层，并且在导电层中形成一个或多个只读存储元件。每个存储元件形成为预定状态，使得它们共同地存储识别用于形成导电层的掩模的数字值。

33. 发明授权

US6097781A Shared counter 失效
公开(公告)号：US6097781A
公开(公告)日：2000-08-01
申请号：US17370
申请日：1998-02-02
申请人： Jeffrey P. Wright , Hua Zheng
发明人： Jeffrey P. Wright , Hua Zheng
IPC分类号： H03K21/00 , G06M3/00
CPC分类号： H03K21/00
摘要： A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

34. 发明授权

US5917762A Circuit and method for providing a substantially constant time delay over a range of supply voltages 失效
公开(公告)号：US5917762A
公开(公告)日：1999-06-29
申请号：US13769
申请日：1998-01-27
申请人： Hua Zheng , Jeffrey P. Wright
发明人： Hua Zheng , Jeffrey P. Wright
IPC分类号： G11C7/10 , G11C7/22 , G11C8/18 , H03K5/13 , H03K5/135 , G11C7/00
CPC分类号： H03K5/133 , G11C7/1072 , G11C7/22 , G11C8/18 , H03K5/135
摘要： A delay circuit provides a substantially constant delay over a range of power-supply voltages. The delay circuit includes an input terminal that receives an input signal, an output terminal that provides an output signal, and a supply terminal that receives a supply voltage. A delay stage is coupled between the input and the output terminals and, when the supply voltage has a predetermined value, generates the output signal a predetermined delay time after it receives the input signal. A control stage is coupled between the supply terminal and the delay stage and regulates the supply current that flows between the supply terminal and the delay stage such that the delay time of the delay stage remains substantially equal to the predetermined delay time as the supply voltage varies from the predetermined value.

35. 发明授权

US08896640B2 Dislplay panel, flat-panel display device and driving method thereof 有权
标题翻译：显示面板，平板显示装置及其驱动方法
公开(公告)号：US08896640B2
公开(公告)日：2014-11-25
申请号：US13578622
申请日：2012-06-13
申请人： Hua Zheng , Cheng-hung Chen
发明人： Hua Zheng , Cheng-hung Chen
IPC分类号： G09G5/10
CPC分类号： G09G5/10 , G09G3/20 , G09G3/2092 , G09G2300/0408 , G09G2310/0281 , G09G2320/0223
摘要： The display panel includes data driven chip and at least two scanning driven chips. The second scanning signal input terminal of each of the scanning driven chip is connected to a first scanning signal output terminal of the data driven chip by corresponding transmission circuits. At least one transmission circuit includes a serially connected resistor so that sum of impedance of the transmission circuits are equal, or the difference of the impedance of the transmission circuit is less than a predetermined value. In addition, a flat-panel display device with uniform brightness and a driving method thereof are also provided.
摘要翻译：显示面板包括数据驱动芯片和至少两个扫描驱动芯片。每个扫描驱动芯片的第二扫描信号输入端通过相应的传输电路连接到数据驱动芯片的第一扫描信号输出端。至少一个传输电路包括串联的电阻器，使得发送电路的阻抗之和相等，或者发送电路的阻抗差小于预定值。此外，还提供了具有均匀亮度的平板显示装置及其驱动方法。

36. 发明申请

US20120060104A1 METHOD AND APPARATUS FOR SHARING VIEWING INFORMATION 有权
标题翻译：共享查看信息的方法和装置
公开(公告)号：US20120060104A1
公开(公告)日：2012-03-08
申请号：US12876964
申请日：2010-09-07
申请人： Eric I. Feng , Hua Zheng , Xin Jin , Zhibing Wang
发明人： Eric I. Feng , Hua Zheng , Xin Jin , Zhibing Wang
IPC分类号： G06F3/048
CPC分类号： H04L65/403 , G06F3/0481 , G06F3/0484 , G06F3/0487 , H04L12/1813 , H04N21/4755 , H04N21/4788 , H04N21/812 , H04N21/8133
摘要： A method and apparatus for sharing viewing information is disclosed. In one embodiment, the method comprises receiving an designation of a second user from the first user; and transmitting the first user viewing information to the designated second user. The shared viewing information may comprise the identity of a currently viewed media program, a list of scheduled media program viewings, or the media program itself.
摘要翻译：公开了一种用于共享观看信息的方法和装置。在一个实施例中，该方法包括从第一用户接收第二用户的指定; 以及将所述第一用户观看信息发送到所述指定的第二用户。共享观看信息可以包括当前所查看的媒体节目的标识，预定的媒体节目观看列表或媒体节目本身。

37. 发明申请

US20080294446A1 Layer based scalable multimedia datastream compression 审中-公开
标题翻译：基于层的可扩展多媒体数据流压缩
公开(公告)号：US20080294446A1
公开(公告)日：2008-11-27
申请号：US11805245
申请日：2007-05-22
申请人： Linfeng Guo , Hua Zheng , Mark Sydorenko , Yang Li
发明人： Linfeng Guo , Hua Zheng , Mark Sydorenko , Yang Li
IPC分类号： G10L19/00
CPC分类号： G10L19/167 , G10L19/0017 , G10L19/0204 , G10L19/24
摘要： Source signals, such as audio and/or video data, are encoded into multiple, consecutive frequency bands. These bands are referred to as coding layers. Rather than performing complex bit-slice operations, a disclosed technique enables an agile and simplified response to transmission channel throughput variations. Specifically, if it becomes necessary to restrict the rate of data transmission to avoid receiver buffer underflow resulting from transmission channel degradation, layers from the transmitted signal are omitted, beginning with the highest frequency bands. Efficient and agile bit rate scalability during data streaming through wired or wireless networks and during local playback is thus enabled.
摘要翻译：诸如音频和/或视频数据的源信号被编码成多个连续的频带。这些频带被称为编码层。所公开的技术不是执行复杂的位片操作，而是能够对传输信道吞吐量变化进行敏捷和简化的响应。具体地，如果需要限制数据传输速率以避免由于传输信道恶化导致的接收机缓冲器下溢，则从最高频带开始，从发送信号中省去层。因此，通过有线或无线网络和本地播放期间的数据流传输期间，高效且敏捷的比特率可扩展性得以实现。

38. 发明授权

US06921827B2 Process for preparing 3-aryl-benzo{b} thiophenes 失效
标题翻译：制备3-芳基 - 苯并{b}噻吩的方法
公开(公告)号：US06921827B2
公开(公告)日：2005-07-26
申请号：US10415569
申请日：2001-11-14
申请人： Wayne Douglas Luke , Heidi Ann Sanderson , Hua Zheng
发明人： Wayne Douglas Luke , Heidi Ann Sanderson , Hua Zheng
IPC分类号： C07D333/52 , C07D333/56 , C07D333/64 , C07D409/00
CPC分类号： C07D333/64 , C07D333/56
摘要： The present invention relates to a process for preparing a compound of formula (I): which includes cyclodehydrating a compound of formula (II): in the presence of an acid activated clay or acid activated zeolite catalyst and in the presence of a suitable solvent
摘要翻译：本发明涉及一种制备式（I）化合物的方法：其包括将式（II）化合物环状脱水：在酸活化的粘土或酸活化的沸石催化剂存在下，并在合适的溶剂

39. 发明授权

US06756805B2 System for testing integrated circuit devices 有权
公开(公告)号：US06756805B2
公开(公告)日：2004-06-29
申请号：US10295499
申请日：2002-11-15
申请人： Joseph C. Sher , David D. Siek , Huy Thanh Vo , Nicholas Van Heel , Victor Wong , Hua Zheng
发明人： Joseph C. Sher , David D. Siek , Huy Thanh Vo , Nicholas Van Heel , Victor Wong , Hua Zheng
IPC分类号： G01R104
CPC分类号： G11C29/02 , G01R31/3004 , G11C5/145 , G11C5/146 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C2029/5004
摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

40. 发明授权

US06288952B1 System for improved memory cell access 有权
标题翻译：用于改进内存单元访问的系统
公开(公告)号：US06288952B1
公开(公告)日：2001-09-11
申请号：US09583040
申请日：2000-05-30
申请人： Hua Zheng
发明人： Hua Zheng
IPC分类号： G11C700
CPC分类号： G11C7/1048 , G11C11/4096
摘要： A voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across the passgate results in faster read and write times and improved noise margin. In one application the booted voltage is used only during a write operation, but not during a read. In another application, the booted voltage is used during both operations.
摘要翻译：用于引导施加到列存取通道的开关信号的电压启动电路用于减小通过门的电压降。降低通过门口的电压降低导致更快的读取和写入时间以及改善的噪声容限。在一个应用中，引导电压仅在写操作期间使用，但不在读取期间使用。在另一个应用中，在两个操作期间都使用引导电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式