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    • 31. 发明授权
    • Single chip adaptive filter utilizing updatable weighting techniques
    • 采用可更新加权技术的单芯片自适应滤波器
    • US5535150A
    • 1996-07-09
    • US388170
    • 1995-02-10
    • Alice M. Chiang
    • Alice M. Chiang
    • H03H21/00G06F17/00
    • H03H21/0012
    • A single chip adaptive filtering system including an finite impulse response (FIR) filter and circuitry for calculating updated weighting coefficients for use in associated multiplying digital-to-analog converters. The adaptive FIR filter performs the convolution of a delayed and sampled input sequence to produce a filter output. Thereafter, an error term is determined by calculating the difference between the filter output and a reference signal which corresponds to a predetermined anticipated output of the filter. The error term is then applied to a least mean square (LMS) estimation algorithm for computing updated weighting coefficients to be used by the adaptive FIR filter.
    • 包括有限脉冲响应(FIR)滤波器和用于计算用于相关联的乘法数模转换器的更新加权系数的电路的单芯片自适应滤波系统。 自适应FIR滤波器执行延迟和采样输入序列的卷积以产生滤波器输出。 此后,通过计算滤波器输出与对应于滤波器的预定预期输出的参考信号之间的差来确定误差项。 然后将误差项应用于用于计算要由自适应FIR滤波器使用的更新的加权系数的最小均方(LMS)估计算法。
    • 32. 发明授权
    • Charge domain vector-matrix product processing system
    • 电荷域矢量矩阵产品处理系统
    • US5089983A
    • 1992-02-18
    • US473870
    • 1990-02-02
    • Alice M. Chiang
    • Alice M. Chiang
    • G06J1/00
    • G06J1/00
    • A charge domain vector-matrix product processing system. The system includes a charge coupled device tapped delay line, an array of digital parallel shift register memory devices, and a signal processor. A sampled analog signal is stored within the tapped delay line, and multiple vectors of m-bit words are stored within the digital memory device. The signal processor sucessively applies vectors from the digital memory device and charge packets from the tapped delay line to an array of digital-analog multipliers. The signal processor then sums the outputs of the digital-analog multipliers and produces an output charge packet corresponding to a respective element of the vector-matrix product.
    • 电荷域向量矩阵乘积处理系统。 该系统包括电荷耦合器件抽头延迟线,数字并行移位寄存器存储器件阵列和信号处理器。 采样的模拟信号被存储在抽头延迟线内,并且m位字的多个向量存储在数字存储器件内。 信号处理器从数字存储设备中过渡地应用向量,并将来自抽头延迟线的数据包充电到数模转换乘法器阵列。 然后,信号处理器对数模转换乘法器的输出进行求和,并产生对应于矢量矩阵积的相应元素的输出电荷数据包。
    • 39. 发明授权
    • Charge domain bit-serial multiplying digital-analog converter
    • 电荷域位串行倍增数字模拟转换器
    • US5555200A
    • 1996-09-10
    • US457827
    • 1995-06-01
    • Alice M. Chiang
    • Alice M. Chiang
    • H03H21/00G06J1/00
    • H03H21/0012
    • A single chip adaptive filtering system including an FIR filter and circuitry for calculating updated weighting coefficients for use in associated multiplying digital-to-analog converters. The adaptive FIR filter performs the convolution of a delayed and sampled input sequence to produce a filter output. Thereafter, an error term is determined by calculating the difference between the filter output and a reference signal which corresponds to a predetermined anticipated output of the filter. The error term is then applied to a least mean square (LMS) estimation algorithm for computing updated weighting coefficients to be used by the adaptive FIR filter.
    • 包括FIR滤波器和用于计算用于相关联的乘法数模转换器的更新加权系数的电路的单芯片自适应滤波系统。 自适应FIR滤波器执行延迟和采样输入序列的卷积以产生滤波器输出。 此后,通过计算滤波器输出与对应于滤波器的预定预期输出的参考信号之间的差来确定误差项。 然后将误差项应用于用于计算要由自适应FIR滤波器使用的更新的加权系数的最小均方(LMS)估计算法。