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31. 发明申请

US20080026551A1 FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SILICIDE PROCESS 失效
标题翻译：使用双自对准硅胶工艺形成全硅酸金属门
公开(公告)号：US20080026551A1
公开(公告)日：2008-01-31
申请号：US11830277
申请日：2007-07-30
申请人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
发明人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
IPC分类号： H01L21/3205
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823443 , H01L29/66545
摘要： An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
摘要翻译：提供了一种先进的栅极结构，其包括硅化金属栅极和硅化源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

32. 发明申请

US20070090471A1 Low threshold voltage semiconductor device with dual threshold voltage control means 有权
标题翻译：具有双阈值电压控制装置的低阈值电压半导体器件
公开(公告)号：US20070090471A1
公开(公告)日：2007-04-26
申请号：US11259644
申请日：2005-10-26
申请人： Eduard Cartier , Mathew Copel , Martin Frank , Evgeni Gousev , Paul Jamison , Rajarao Jammy , Barry Linder , Vijay Narayanan
发明人： Eduard Cartier , Mathew Copel , Martin Frank , Evgeni Gousev , Paul Jamison , Rajarao Jammy , Barry Linder , Vijay Narayanan
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28238 , H01L21/823807 , H01L29/105 , H01L29/1083 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
摘要翻译：一种半导体结构，特别是pFET，其包括介电常数大于SiO 2的介电常数和大于50％的Ge或Si含量的至少一种其它装置，提供材料堆栈工程的阈值/平带电压调谐。本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。本发明还涉及一种制造这种CMOS结构的方法。

33. 发明申请

US20050258491A1 Threshold and flatband voltage stabilization layer for field effect transistors with high permittivity gate oxides 审中-公开
标题翻译：具有高介电常数栅氧化物的场效应晶体管的阈值和平带电压稳定层
公开(公告)号：US20050258491A1
公开(公告)日：2005-11-24
申请号：US10845719
申请日：2004-05-14
申请人： Nestor Bojarczuk , Eduard Cartier , Martin Frank , Evgeni Gousev , Supratik Guha , Vijay Narayanan
发明人： Nestor Bojarczuk , Eduard Cartier , Martin Frank , Evgeni Gousev , Supratik Guha , Vijay Narayanan
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/786 , H01L51/00 , H01L51/05
CPC分类号： H01L21/28202 , H01L21/28194 , H01L21/823857 , H01L29/4916 , H01L29/513 , H01L29/517 , H01L29/518
摘要： An insulating interlayer for use in complementary metal oxide semiconductor (CMOS) that prevents unwanted shifts in threshold voltage and flatband voltage is provided. The insulating interlayer is located between a gate dielectric having a dielectric constant of greater than 4.0 and a Si-containing gate conductor. The insulating interlayer of the present invention is any metal nitride, that optionally may include oxygen, that is capable of stabilizing the threshold and flatband voltages. In a preferred embodiment, the insulating interlayer is aluminum nitride or aluminum oxynitride and the gate dielectric is hafnium oxide, hafnium silicate or hafnium silicon oxynitride. The present invention is particularly useful in stabilizing the threshold and flatband voltage of p-type field effect transistors.
摘要翻译：提供了用于防止阈值电压和平带电压的不期望的偏移的互补金属氧化物半导体（CMOS）中的绝缘夹层。绝缘中间层位于介电常数大于4.0的栅极电介质和含Si的栅极导体之间。本发明的绝缘中间层是能够稳定阈值和平带电压的任何金属氮化物，其可任选地包括氧。在优选实施例中，绝缘中间层为氮化铝或氮氧化铝，栅极电介质为氧化铪，硅酸铪或铪硅氮氧化物。本发明在稳定p型场效应晶体管的阈值和平带电压方面特别有用。

34. 发明申请

US20050026459A1 Method of forming uniform ultra-thin oxynitride layers 有权
标题翻译：形成均匀的超薄氧氮化物层的方法
公开(公告)号：US20050026459A1
公开(公告)日：2005-02-03
申请号：US10630970
申请日：2003-07-31
申请人： David O'Meara , Cory Wajda , Anthony Dip , Michael Toeller , Toshihara Furukawa , Kristen Scheer , Alessandro Callegari , Fred Buehrer , Sufi Zafar , Evgeni Gousev , Anthony Chou , Paul Higgins
发明人： David O'Meara , Cory Wajda , Anthony Dip , Michael Toeller , Toshihara Furukawa , Kristen Scheer , Alessandro Callegari , Fred Buehrer , Sufi Zafar , Evgeni Gousev , Anthony Chou , Paul Higgins
IPC分类号： C23C16/30 , H01L21/00 , H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28185 , C23C16/308 , H01L21/0214 , H01L21/02238 , H01L21/02249 , H01L21/02255 , H01L21/28202 , H01L21/3144 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L21/67098 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.
摘要翻译：使用低压处理形成超薄氧氮化物层，以实现衬底的自限制氧化并提供超薄氧氮化物。要处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层或氮化物层，或者可以缺少初始介电层。处理可以使用间歇式处理室或单晶片处理室进行。

35. 发明授权

US08536059B2 Equipment and methods for etching of MEMS 失效
标题翻译：用于蚀刻MEMS的设备和方法
公开(公告)号：US08536059B2
公开(公告)日：2013-09-17
申请号：US12527864
申请日：2008-02-18
申请人： Khurshid Syed Alam , Evgeni Gousev , Marc Maurice Mignard , David Heald , Ana R. Londergan , Philip Don Floyd
发明人： Khurshid Syed Alam , Evgeni Gousev , Marc Maurice Mignard , David Heald , Ana R. Londergan , Philip Don Floyd
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/67069 , B81B2201/047 , B81C1/00531
摘要： Etching equipment and methods are disclosed herein for more efficient etching of sacrificial material from between permanent MEMS structures. An etching head includes an elongate etchant inlet structure, which may be slot-shaped or an elongate distribution of inlet holes. A substrate is supported in proximity to the etching head in a manner that defines a flow path substantially parallel to the substrate face, and permits relative motion for the etching head to scan across the substrate.
摘要翻译：本文公开了蚀刻设备和方法，用于从永久MEMS结构之间更有效地蚀刻牺牲材料。蚀刻头包括细长的蚀刻剂入口结构，其可以是槽形的或入口孔的细长分布。衬底以限定基本上平行于衬底面的流动路径的方式支撑在蚀刻头附近，并且允许蚀刻头相对于衬底扫描的相对运动。

36. 发明申请

US20130003158A1 APPARATUS AND METHOD FOR OPTICAL DECOUPLING 审中-公开
标题翻译：光学解除装置和方法
公开(公告)号：US20130003158A1
公开(公告)日：2013-01-03
申请号：US13171245
申请日：2011-06-28
申请人： Evgeni Gousev , Russell Wayne Gruhlke
发明人： Evgeni Gousev , Russell Wayne Gruhlke
IPC分类号： G02B26/00 , B05D3/00 , B23P11/00 , B05D5/06
CPC分类号： G02B26/001 , Y10T29/49826
摘要： This disclosure provides apparatus, systems and methods for optical decoupling. In one implementation, an optical system includes a substrate transmissive to visible light, a first antireflective structure disposed on a surface of the substrate, a second antireflective structure. The first and second antireflective structures define at least one cavity containing air in between. The optical system further includes a plurality of support posts configured to space the first antireflective structure from the second antireflective structure to define the height of the at least one cavity. A reflective display is disposed on a surface of the second antireflective structure opposite the at least one cavity.
摘要翻译：本公开提供了用于光学去耦的装置，系统和方法。在一个实施方案中，光学系统包括透射可见光的衬底，设置在衬底的表面上的第一抗反射结构，第二抗反射结构。第一和第二抗反射结构限定了至少一个容纳空气的空腔。光学系统还包括多个支撑柱，其被配置为将第一抗反射结构与第二抗反射结构间隔开以限定至少一个腔的高度。反射显示器设置在与至少一个空腔相对的第二抗反射结构的表面上。

37. 发明授权

US08323516B2 Etching processes used in MEMS production 失效
标题翻译：用于MEMS生产的蚀刻工艺
公开(公告)号：US08323516B2
公开(公告)日：2012-12-04
申请号：US12210042
申请日：2008-09-12
申请人： Ion Bita , Evgeni Gousev , Ana Londergan , Xiaoming Yan
发明人： Ion Bita , Evgeni Gousev , Ana Londergan , Xiaoming Yan
IPC分类号： H01B13/00
CPC分类号： H01L21/32135 , B01D53/002 , B01D2257/11 , B01D2257/2027 , H01L21/31116
摘要： The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.
摘要翻译：可以以各种方式增加蚀刻工艺的效率，并且可以降低蚀刻工艺的成本。未蚀刻的蚀刻剂可以在蚀刻过程中被隔离并再循环。蚀刻副产物可以在蚀刻过程中从蚀刻系统中收集和去除。蚀刻剂的组分可以被分离并用于一般的另外的蚀刻剂。蚀刻剂或被蚀刻的层中的任一个或两者也可以针对特定的蚀刻工艺进行优化。

38. 发明授权

US07978395B2 Capacitive MEMS device with programmable offset voltage control 有权
标题翻译：具有可编程失调电压控制的电容式MEMS器件
公开(公告)号：US07978395B2
公开(公告)日：2011-07-12
申请号：US12789195
申请日：2010-05-27
申请人： Daniel Felnhofer , Evgeni Gousev
发明人： Daniel Felnhofer , Evgeni Gousev
IPC分类号： G02B26/00 , G02B26/02
CPC分类号： B81B3/0086 , B81B2201/045 , G02B26/001 , G11C23/00
摘要： A capacitive MEMS device is formed having a material between electrodes that traps and retains charges. The material can be realized in several configurations. It can be a multilayer dielectric stack with regions of different band gap energies or band energy levels. The dielectric materials can be trappy itself, i.e. when defects or trap sites are pre-fabricated in the material. Another configuration involves a thin layer of a conductive material with the energy level in the forbidden gap of the dielectric layer. The device may be programmed (i.e. offset and threshold voltages pre-set) by a method making advantageous use of charge storage in the material, wherein the interferometric modulator is pre-charged in such a way that the hysteresis curve shifts, and the actuation voltage threshold of the modulator is significantly lowered. During programming phase, charge transfer between the electrodes and the materials can be performed by applying voltage to the electrodes (i.e. applying electrical field across the material) or by UV-illumination and injection of electrical charges over the energy barrier. The interferometric modulator may then be retained in an actuated state with a significantly lower actuation voltage, thereby saving power.
摘要翻译：形成电容MEMS器件，其具有陷阱并保持电荷的电极之间的材料。该材料可以在几种配置中实现。它可以是具有不同带隙能量或带能级的区域的多层电介质叠层。电介质材料本身可以是歪斜的，即当在材料中预先制造缺陷或捕获位置时。另一种结构涉及导电材料的薄层，其中电介质层的禁止间隙具有能级。可以通过有利地使用材料中的电荷存储的方法来对器件进行编程（即，偏移和阈值电压预设），其中干涉式调制器以滞后曲线偏移的方式预充电，并且致动电压调制器的阈值显着降低。在编程阶段期间，电极和材料之间的电荷转移可以通过向电极施加电压（即跨越材料施加电场）或通过UV照射和在能量屏障上注入电荷来执行。然后干涉式调制器可以以明显更低的致动电压保持在致动状态，从而节省功率。

39. 发明申请

US20100245979A1 MEMS CAVITY-COATING LAYERS AND METHODS 有权
标题翻译： MEMS CAVAY-COATING LAYERS AND METHODS
公开(公告)号：US20100245979A1
公开(公告)日：2010-09-30
申请号：US12795294
申请日：2010-06-07
申请人： Ana R. Londergan , Bangalore R. Natarajan , Evgeni Gousev , James Randolph Webster , David Heald
发明人： Ana R. Londergan , Bangalore R. Natarajan , Evgeni Gousev , James Randolph Webster , David Heald
IPC分类号： G02B26/00
CPC分类号： G02B26/001 , B81B3/0008 , B81B2201/047
摘要： Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties.
摘要翻译：包括MEMS器件（例如干涉式调制器）的器件，方法和系统，其包括其中层涂覆多个表面的空腔。该层是保形的或非保形的。在一些实施例中，该层由原子层沉积（ALD）形成。优选地，该层包括电介质材料。在一些实施例中，MEMS器件还表现出改进的特性，例如移动电极之间的改善的电绝缘性，降低的静摩擦力和/或改善的机械性能。

40. 发明申请

US20100238537A1 CAPACITIVE MEMS DEVICE WITH PROGRAMMABLE OFFSET VOLTAGE CONTROL 有权
标题翻译：具有可编程偏移电压控制的电容式MEMS器件
公开(公告)号：US20100238537A1
公开(公告)日：2010-09-23
申请号：US12789195
申请日：2010-05-27
申请人： Daniel Felnhofer , Evgeni Gousev
发明人： Daniel Felnhofer , Evgeni Gousev
IPC分类号： G02B26/00 , C23C14/22
CPC分类号： B81B3/0086 , B81B2201/045 , G02B26/001 , G11C23/00
摘要： A capacitive MEMS device is formed having a material between electrodes that traps and retains charges. The material can be realized in several configurations. It can be a multilayer dielectric stack with regions of different band gap energies or band energy levels. The dielectric materials can be trappy itself, i.e. when defects or trap sites are pre-fabricated in the material. Another configuration involves a thin layer of a conductive material with the energy level in the forbidden gap of the dielectric layer. The device may be programmed (i.e. offset and threshold voltages pre-set) by a method making advantageous use of charge storage in the material, wherein the interferometric modulator is pre-charged in such a way that the hysteresis curve shifts, and the actuation voltage threshold of the modulator is significantly lowered. During programming phase, charge transfer between the electrodes and the materials can be performed by applying voltage to the electrodes (i.e. applying electrical field across the material) or by UV-illumination and injection of electrical charges over the energy barrier. The interferometric modulator may then be retained in an actuated state with a significantly lower actuation voltage, thereby saving power.
摘要翻译：形成电容MEMS器件，其具有陷阱并保持电荷的电极之间的材料。该材料可以在几种配置中实现。它可以是具有不同带隙能量或带能级的区域的多层电介质叠层。电介质材料本身可以是歪斜的，即当在材料中预先制造缺陷或捕获位置时。另一种结构涉及导电材料的薄层，其中电介质层的禁止间隙具有能级。可以通过有利地使用材料中的电荷存储的方法来对器件进行编程（即，偏移和阈值电压预设），其中干涉式调制器以滞后曲线偏移的方式预充电，并且致动电压调制器的阈值显着降低。在编程阶段期间，电极和材料之间的电荷转移可以通过向电极施加电压（即跨越材料施加电场）或通过UV照射和在能量屏障上注入电荷来执行。然后干涉式调制器可以以明显更低的致动电压保持在致动状态，从而节省功率。

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