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    • 34. 发明授权
    • Forced substrate test mode for packaged integrated circuits
    • 用于封装集成电路的强制衬底测试模式
    • US5212442A
    • 1993-05-18
    • US854485
    • 1992-03-20
    • James E. O'TooleBrian P. Higgins
    • James E. O'TooleBrian P. Higgins
    • G01R31/30G01R31/317G11C29/50
    • G01R31/30G01R31/31701G11C29/50G11C11/401G11C11/41
    • An integrated circuit such as an SRAM or DRAM fabricated in a package having a number of external pins includes a plurality of inputs and outputs electrically coupled to the external package pins, an internal substrate that is unconnected to any of the external pins, a test mode indicator circuit having an input coupled to an external pin and an output for providing a test mode signal and a switch responsive to the test mode signal for coupling the substrate to a predetermined voltage. The predetermined voltage can either be ground, or a negative voltage introduced on a pin that is normally set to a logic zero during package level testing. The test mode signal can also be used to disable the on-chip charge pump. The test mode indicator circuit can include a super voltage indicator, an electronic key, or latch circuit in order to receive the test mode indication signal on an existing package pin.
    • 在具有多个外部引脚的封装中制造的诸如SRAM或DRAM的集成电路包括电耦合到外部封装引脚的多个输入和输出,未连接到任何外部引脚的内部基板,测试模式 指示器电路具有耦合到外部引脚的输入和用于提供测试模式信号的输出和响应于测试模式信号的开关,用于将基板耦合到预定电压。 预定电压可以被接地,也可以是在封装级测试期间通常设置为逻辑0的引脚上的负电压。 测试模式信号也可用于禁用片上电荷泵。 测试模式指示器电路可以包括超电压指示器,电子钥匙或锁存电路,以便在现有封装引脚上接收测试模式指示信号。