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31. 发明授权

US07155561B2 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US07155561B2
公开(公告)日：2006-12-26
申请号：US11230836
申请日：2005-09-19
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison
IPC分类号： G06F12/16
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

32. 发明申请

US20060265565A1 Dual edge command 有权
公开(公告)号：US20060265565A1
公开(公告)日：2006-11-23
申请号：US11495418
申请日：2006-07-28
申请人： Joo Choi , Troy Manning , Brent Keeth
发明人： Joo Choi , Troy Manning , Brent Keeth
IPC分类号： G06F13/00
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

33. 发明申请

US20060045206A1 Method and system for generating reference voltages for signal receivers 有权
公开(公告)号：US20060045206A1
公开(公告)日：2006-03-02
申请号：US10930543
申请日：2004-08-30
申请人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
IPC分类号： H04L27/06
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

34. 发明申请

US20060044891A1 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US20060044891A1
公开(公告)日：2006-03-02
申请号：US10931472
申请日：2004-08-31
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

35. 发明授权

US06948027B2 Method and system for using dynamic random access memory as cache memory 失效
公开(公告)号：US06948027B2
公开(公告)日：2005-09-20
申请号：US10815877
申请日：2004-03-30
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G11C7/10 , G11C11/406 , G11C11/409 , G11C15/04 , G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

36. 发明授权

US06934173B2 256 Meg dynamic random access memory 失效
标题翻译： 256 Meg动态随机存取存储器
公开(公告)号：US06934173B2
公开(公告)日：2005-08-23
申请号：US09893389
申请日：2001-06-28
申请人： Brent Keeth , Layne G. Bunker , Scott J. Derner
发明人： Brent Keeth , Layne G. Bunker , Scott J. Derner
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

37. 发明授权

US06930955B2 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM 失效
标题翻译：用于在高速DRAM中建立和维持期望的读延迟的方法和装置
公开(公告)号：US06930955B2
公开(公告)日：2005-08-16
申请号：US10851081
申请日：2004-05-24
申请人： Brian Johnson , Brent Keeth , Feng Lin
发明人： Brian Johnson , Brent Keeth , Feng Lin
IPC分类号： G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4076
CPC分类号： G11C7/222 , G11C7/1072 , G11C11/4076
摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.
摘要翻译：一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。内部读延迟值用于抵消DRAM电路的内部读延迟。一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

38. 发明授权

US06850452B2 256 Meg dynamic random access memory 失效
公开(公告)号：US06850452B2
公开(公告)日：2005-02-01
申请号：US10106558
申请日：2002-03-22
申请人： Brent Keeth , Layne G. Bunker
发明人： Brent Keeth , Layne G. Bunker
IPC分类号： G11C5/02 , G11C5/06 , H01L27/108 , G11C7/00
CPC分类号： H01L27/10805 , G11C5/025 , G11C5/063
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

39. 发明授权

US06839265B2 Bi-level digit line architecture for high density DRAMS 失效
标题翻译：用于高密度DRAMS的双级数字线路架构
公开(公告)号：US06839265B2
公开(公告)日：2005-01-04
申请号：US10440575
申请日：2003-05-19
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： H01L21/8242 , H01L23/522 , H01L27/108 , G11C5/06
CPC分类号： H01L27/10885 , H01L23/5225 , H01L27/10897 , H01L2924/0002 , H01L2924/3011 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： There is provided a bi-level bit line architecture. Specifically, a DRAM memory cell and cell array are provided that allow for six square feature area (6F2) cell sizes and avoid the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double-decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.
摘要翻译：提供了双级位线架构。具体地，提供了允许六个正方形特征区域（6F 2）单元尺寸的DRAM存储单元和单元阵列，并且避免了信噪比问题。独特的是，数字线条设计成像双层天桥路一样躺在彼此之上。此外，该设计允许每个数字线路在两个导体层上布线，对于阵列的相同长度，以提供平衡阻抗。现在噪声将作为两条线路上的共模噪声出现，而不是会降低感测操作的差模噪声。此外，由于扭转设计，数字到数字耦合几乎消除了。

40. 发明授权

US06757200B2 Semiconductor memory having dual port cell supporting hidden refresh 失效
标题翻译：具有双端口单元的半导体存储器支持隐藏刷新
公开(公告)号：US06757200B2
公开(公告)日：2004-06-29
申请号：US10269599
申请日：2002-10-10
申请人： Brent Keeth , Charles Dennison
发明人： Brent Keeth , Charles Dennison
IPC分类号： G11C700
CPC分类号： G11C11/403 , G11C11/406 , Y10S257/907
摘要： The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.
摘要翻译：本发明涉及具有用于存储数据的存储单元的集成电路装置和用于刷新存储单元中的数据的刷新电路。在一个说明性实施例中，该设备包括具有存储元件，读/写访问设备和刷新访问设备的存储单元。读/写数字线耦合到读/写访问设备，并且刷新数字线耦合到刷新访问设备。读出放大器耦合到读/写数字线，并且输入/输出电路耦合到读/写数字线。刷新读出放大器耦合到刷新数字线。存储单元被构造成在相对较小，紧凑的区域中提供大的电荷存储容量。

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