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    • 33. 发明授权
    • Method of manufacturing a display substrate
    • 制造显示基板的方法
    • US08476093B2
    • 2013-07-02
    • US13166706
    • 2011-06-22
    • Jung-Soo LeeJeong-Min ParkJi-Hyun Kim
    • Jung-Soo LeeJeong-Min ParkJi-Hyun Kim
    • H01L33/36
    • H01L27/1288
    • A method of manufacturing a display substrate includes forming a common electrode line, a gate line, a data line and a switching element connected to the gate and data lines on an insulation substrate. A first pixel electrode and an insulation layer are sequentially formed on the insulation substrate. A first photoresist pattern having a first hole and a second hole is formed from a first photoresist layer on the insulation substrate. A first transparent electrode layer is coated on the insulation substrate. A second photoresist layer is coated on the insulation substrate. The second photoresist layer is exposed and developed to form a second photoresist pattern remaining in the first hole and the second hole. The first transparent electrode layer is patterned using the second photoresist pattern, to form a second pixel electrode.
    • 制造显示基板的方法包括在绝缘基板上形成公共电极线,栅极线,数据线以及连接到栅极和数据线的开关元件。 第一像素电极和绝缘层依次形成在绝缘基板上。 具有第一孔和第二孔的第一光致抗蚀剂图案由绝缘基板上的第一光致抗蚀剂层形成。 第一透明电极层涂覆在绝缘基板上。 第二光致抗蚀剂层涂覆在绝缘基板上。 第二光致抗蚀剂层被曝光和显影以形成保留在第一孔和第二孔中的第二光致抗蚀剂图案。 使用第二光致抗蚀剂图案对第一透明电极层进行构图,以形成第二像素电极。
    • 35. 发明申请
    • DIGITAL PHASE FREQUENCY DETECTOR, DIGITAL PHASE LOCKED LOOP INCLUDING THE SAME AND METHOD OF DETECTING PHASE AND FREQUENCY OF OUTPUT SIGNAL
    • 数字相位频率检测器,数字相位锁定环路及其相位检测和输出信号频率检测方法
    • US20120183104A1
    • 2012-07-19
    • US13315476
    • 2011-12-09
    • JONG-PHIL HONGJi-Hyun KimJae-Jin Park
    • JONG-PHIL HONGJi-Hyun KimJae-Jin Park
    • H04L27/06
    • H03L7/113H03L7/085H03L7/1077
    • A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.
    • 数字相位频率检测器包括检测单元,复位单元和相位比较单元。 检测单元检测参考信号和反馈输入信号的边沿以产生参考边缘信号和反馈边缘信号。 复位单元基于参考边沿信号和反馈边沿信号产生复位检测单元的复位信号。 相位比较单元基于参考边缘信号和反馈边缘信号产生第一和第二相位比较信号。 相位比较单元包括基于参考边缘信号和反馈边缘信号产生第一比较信号的第一触发器,基于参考边缘信号和反馈边缘信号产生第二比较信号的第二触发器,以及 锁存块锁存第一和第二比较信号以产生第一和第二相位比较信号。
    • 40. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08035442B2
    • 2011-10-11
    • US11645949
    • 2006-12-27
    • Ji-Hyun Kim
    • Ji-Hyun Kim
    • H03K3/01
    • G11C16/30G11C5/145
    • A semiconductor device including a pumping capacitor for inducing a high voltage, a switching circuit for transferring the high voltage induced by the pumping capacitor and a switching control circuit for controlling the switching circuit, wherein the switching control circuit includes a first capacitor for inducing a switching control voltage to a first node in response to an oscillation signal, a first switching MOS transistor for transferring the switching control voltage applied to the first node to a second node, and a first turn-on controller for maintaining the first switching MOS transistor to be turned on, and allowing a voltage below a predetermined voltage difference to be applied between the first node and a gate of the first switching MOS transistor.
    • 一种包括用于感应高电压的泵浦电容器的半导体器件,用于传送由泵浦电容器感应的高电压的开关电路和用于控制开关电路的开关控制电路,其中开关控制电路包括用于引起开关的第一电容器 响应于振荡信号控制到第一节点的电压;第一开关MOS晶体管,用于将施加到第一节点的开关控制电压传递到第二节点;以及第一导通控制器,用于将第一开关MOS晶体管保持为 导通,并且允许在第一开关MOS晶体管的第一节点和栅极之间施加低于预定电压差的电压。