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    • 36. 发明授权
    • Highly integrated semiconductor device and method of fabricating the same
    • 高度集成的半导体器件及其制造方法
    • US07803697B2
    • 2010-09-28
    • US11600719
    • 2006-11-17
    • Sung-Min KimEun-Jung Yun
    • Sung-Min KimEun-Jung Yun
    • H01L21/20
    • H01L27/24
    • A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline semiconductor layer on the substrate, the semiconductor layer contacting the second pattern and the exposed portion of the substrate, and, using the substrate as a seed layer, changing the crystalline state of the semiconductor layer to be single-crystalline and changing the crystalline state of the second pattern to be single-crystalline.
    • 一种制造半导体器件的方法包括在衬底上顺序地形成第一图案和第二图案,第二图案是堆叠在第一图案上的非单晶半导体,其中衬底的一部分暴露在与第一图案相邻的第一图案 和第二图案,在衬底上形成非单晶半导体层,与第二图案接触的半导体层和衬底的暴露部分,并且使用衬底作为种子层,改变半导体层的结晶状态 为单晶,并将第二图案的结晶状态改变为单晶。
    • 37. 发明申请
    • SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF
    • 肖特基屏障器件及其制造方法
    • US20100197099A1
    • 2010-08-05
    • US12759290
    • 2010-04-13
    • Sung-Min KimEun-Jung YunDong-Won Kim
    • Sung-Min KimEun-Jung YunDong-Won Kim
    • H01L21/336
    • H01L29/41791H01L29/66795H01L29/7839H01L29/78618H01L29/78684
    • A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
    • 提供肖特基势垒FinFET器件及其制造方法。 该装置包括设置在基板上的下部翅片体。 提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。 提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。 肖特基势垒FinFET器件包括源极和漏极,其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上,并且由形成在位于两侧的下翅片体的上表面上的金属材料层 并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。
    • 38. 发明申请
    • SEMICONDUCTOR DEVICE INCLUDING A CRYSTAL SEMICONDUCTOR LAYER, ITS FABRICATION AND ITS OPERATION
    • 半导体器件,包括晶体半导体层,其制造及其操作
    • US20100148260A1
    • 2010-06-17
    • US12710378
    • 2010-02-23
    • Sung-Min KimEun-Jung Yun
    • Sung-Min KimEun-Jung Yun
    • H01L29/786
    • H01L21/02667H01L21/02639H01L21/2026H01L27/108H01L27/10802H01L27/10826H01L27/10879H01L29/66795H01L29/785
    • In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.
    • 在一个实施例中,制造具有晶体半导体层的半导体器件的方法包括制备半导体衬底并在半导体衬底上形成预活性图案。 预活性图案包括阻挡图案和非单晶半导体图案。 牺牲非单晶半导体层覆盖预活性图案和半导体衬底。 通过使牺牲非单晶半导体层和非单晶半导体图案结晶,使用半导体衬底作为晶种层,将牺牲非单晶半导体层和非单晶半导体图案改变为牺牲晶体 半导体层和晶体半导体图案。 晶体半导体图案和势垒图案构成活性图案。 去除牺牲晶体半导体层。
    • 39. 发明申请
    • Methods of Fabricating Electromechanical Non-Volatile Memory Devices
    • 制造机电非易失性存储器件的方法
    • US20100129976A1
    • 2010-05-27
    • US12693783
    • 2010-01-26
    • Eun Jung YunSung-Young LeeMin-Sang KimSung-Min Kim
    • Eun Jung YunSung-Young LeeMin-Sang KimSung-Min Kim
    • H01L21/02
    • H01L27/10G11C23/00
    • Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided.
    • 提供了包括具有包括绝缘特性的上表面的半导体衬底的机电非易失性存储器件。 第一电极图案设置在半导体衬底上。 第一电极图案暴露半导体衬底的表面的部分通过其中。 在第一电极图案和半导体衬底的暴露表面上提供保形位线。 位线与第一电极图案的侧壁间隔开,并且包括具有由电压差产生的弹性的导电材料。 绝缘层图案设置在位于半导体衬底上的位线的上表面上。 第二电极图案与位线间隔开并设置在绝缘层图案上。 第二电极图案面向第一电极图案。 还提供了相关方法。