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31. 发明授权

US10127184B2 Low overheard high throughput solution for point-to-point link 有权
公开(公告)号：US10127184B2
公开(公告)日：2018-11-13
申请号：US15277893
申请日：2016-09-27
申请人： INTEL CORPORATION
发明人： Eng Hun Ooi , Su Wei Lim
IPC分类号： H03M13/11 , G06F13/42 , G06F11/10 , G06F11/34 , G06F11/30
摘要： An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.

32. 发明申请

US20160034345A1 MEMORY LATENCY MANAGEMENT 有权
标题翻译：内存管理
公开(公告)号：US20160034345A1
公开(公告)日：2016-02-04
申请号：US14775848
申请日：2014-02-26
申请人： Robert J. ROYER, JR. , Blaise FANNING , Eng Hun OOI , INTEL CORPORATION
发明人： Robert J. Royer, Jr. , Blaise Fanning , Eng Hun Ooi
IPC分类号： G06F11/10 , G06F12/08
CPC分类号： G06F11/1064 , G06F11/1048 , G06F12/084 , G06F12/0866 , G06F2212/1032 , G06F2212/313
摘要： Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
摘要翻译：描述了用于管理存储器延迟操作的装置，系统和方法。在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，以及实现数据管理策略响应于纠错码指示器。还公开并要求保护其他实施例。

33. 发明授权

US09116694B2 Efficient low power exit sequence for peripheral devices 有权
标题翻译：外围设备的低功耗退出顺序
公开(公告)号：US09116694B2
公开(公告)日：2015-08-25
申请号：US13627779
申请日：2012-09-26
申请人： Intel Corporation
发明人： Eng Hun Ooi
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/325 , G06F1/3268 , Y02D10/154 , Y02D50/20
摘要： Embodiments of the invention describe methods, apparatuses and systems for providing an efficient low power exit sequence for peripheral devices. In embodiments of the invention, a signal from a host device is transmitted to a SATA peripheral device for exiting a low-power state. An initialization time for OOB transmission and reception logic of the SATA peripheral device is tracked, and a reference time value based on the tracked initialization time is stored. In subsequent transitions from said low-power state, the reference time value for waking a host physical layer is utilized, thereby improving the efficiency of the management and use of said low power state. In some embodiments, the above described tracked initialization comprises a time from a transmission of an OOB signal (from the host to the peripheral device) to receiving an OOB response at the host device from the SATA peripheral device.
摘要翻译：本发明的实施例描述了用于为外围设备提供有效的低功率出口序列的方法，装置和系统。在本发明的实施例中，来自主机设备的信号被传送到SATA外围设备以退出低功率状态。跟踪SATA外围设备的OOB发送和接收逻辑的初始化时间，并且存储基于追踪的初始化时间的基准时间值。在从所述低功率状态的后续转换中，利用用于唤醒主机物理层的参考时间值，从而提高所述低功率状态的管理和使用的效率。在一些实施例中，上述跟踪的初始化包括从OOB信号（从主机到外围设备）的传输到在主机设备处从SATA外围设备接收OOB响应的时间。

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