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31. 发明授权

US07157770B2 MOS transistor with recessed gate and method of fabricating the same 失效
标题翻译：具有凹陷栅极的MOS晶体管及其制造方法
公开(公告)号：US07157770B2
公开(公告)日：2007-01-02
申请号：US10884223
申请日：2004-07-01
申请人： Jong-Chul Park , Jong-Heui Song
发明人： Jong-Chul Park , Jong-Heui Song
IPC分类号： H01L29/76
CPC分类号： H01L29/66621 , H01L21/823437 , H01L21/823481 , H01L21/823487 , H01L27/10876 , H01L29/66537 , H01L29/7835
摘要： A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.
摘要翻译：具有凹陷栅极的MOS晶体管及其制造方法：MOS晶体管包括半导体衬底和位于半导体衬底的用于限定有源区的预定区域中的沟槽隔离层。沟槽隔离层在至少其下侧壁上具有负斜率。凹入栅极位于有源区的预定区域中，并且凹入栅极的底表面邻近沟槽隔离层的负斜面侧壁放置。

32. 发明申请

US20060113590A1 Method of forming a recess structure, recessed channel type transistor and method of manufacturing the recessed channel type transistor 审中-公开
标题翻译：形成凹陷结构的方法，凹槽型晶体管和制造凹槽型晶体管的方法
公开(公告)号：US20060113590A1
公开(公告)日：2006-06-01
申请号：US11285558
申请日：2005-11-22
申请人： Ji-Hae Kim , Ji-Young Kim , Jong-Chul Park , Yong-Sun Ko , Sang-Sup Jeong
发明人： Ji-Hae Kim , Ji-Young Kim , Jong-Chul Park , Yong-Sun Ko , Sang-Sup Jeong
IPC分类号： H01L29/94
CPC分类号： H01L29/66621 , H01L29/7834
摘要： An isolation layer having a first depth is formed from an upper face of a substrate. Source/drain regions including junctions are formed in the substrate. Each of the junctions has a second depth substantially smaller than the first depth. A first recess is formed in the substrate by a first etching process. A protection layer pattern is formed on a sidewall of the first recess. A second recess is formed beneath the first recess. The second recess has a width substantially larger than that of the first recess. The second recess is formed by a second etching process using an etching gas containing an SF6 gas, a Cl2 gas and an O2 gas. A gate insulation layer is formed on surfaces of the first and the second recesses. The second recess having an enlarged shape may reduce a width of the junction between the gate electrode and the isolation layer so that a leakage current generated through the junction may decrease.
摘要翻译：具有第一深度的隔离层由衬底的上表面形成。在衬底中形成包括结的源/漏区。每个结点具有比第一深度基本上小的第二深度。通过第一蚀刻工艺在衬底中形成第一凹部。在第一凹部的侧壁上形成保护层图案。在第一凹部下面形成第二凹部。第二凹部的宽度显着大于第一凹部的宽度。第二凹槽通过使用含有SF 6气体，Cl 2气体和O 2气体的蚀刻气体的第二蚀刻工艺形成。在第一和第二凹部的表面上形成栅极绝缘层。具有放大形状的第二凹部可以减小栅电极和隔离层之间的结的宽度，使得通过结可以产生的漏电流可能减小。

33. 发明申请

US20050277254A1 Methods of forming device with recessed gate electrodes 有权
标题翻译：具有凹陷栅电极的器件形成方法
公开(公告)号：US20050277254A1
公开(公告)日：2005-12-15
申请号：US11148760
申请日：2005-06-09
申请人： Jae-Kyu Ha , Jong-Chul Park
发明人： Jae-Kyu Ha , Jong-Chul Park
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8242
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876
摘要： Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active region. A hard mask layer is formed with a substantially planar upper surface on the field region and the active region. The hard mask layer is partially etched to form a hard mask pattern that exposes at least a portion of the active region. The substrate is partially etched in the active region using the hard mask pattern as an etching mask to form a gate trench. A recessed gate electrode if formed on the substrate in the gate trench.
摘要翻译：提供了用于形成诸如半导体器件的器件的方法。定义了场区域和衬底的有源区域，其中场区域具有远离衬底延伸的上表面并且高于有源区域的上表面。硬掩模层在场区域和有源区域上形成有基本平坦的上表面。硬掩模层被部分蚀刻以形成暴露至少一部分有源区的硬掩模图案。使用硬掩模图案作为蚀刻掩模在有源区中部分地蚀刻衬底以形成栅极沟槽。如果形成在栅极沟槽中的衬底上的凹陷栅电极。

34. 发明申请

US20050196921A1 Method of forming capacitor over bitline contact 有权
标题翻译：通过位线接触形成电容器的方法
公开(公告)号：US20050196921A1
公开(公告)日：2005-09-08
申请号：US11033447
申请日：2005-01-12
申请人： Yong-Woo Lee , Jong-Chul Park , O-Ik Kwon , Sang-Sup Jeong
发明人： Yong-Woo Lee , Jong-Chul Park , O-Ik Kwon , Sang-Sup Jeong
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/4763 , H01L21/8242
CPC分类号： H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.
摘要翻译：一种通过在其上形成有第一焊盘和第二焊盘的半导体衬底中形成存储节点接触来形成半导体器件的接触的方法。存储节点触点连接到第二焊盘。与存储节点接触的位线通过间隔物电绝缘并电连接到第一焊盘。

35. 发明授权

US09159767B2 Methods of manufacturing magnetoresistive random access memory devices 有权
标题翻译：制造磁阻随机存取存储器件的方法
公开(公告)号：US09159767B2
公开(公告)日：2015-10-13
申请号：US14182316
申请日：2014-02-18
申请人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
发明人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
IPC分类号： H01L43/12 , H01L27/22
CPC分类号： H01L27/228 , G11C11/161 , H01L43/12
摘要： In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.
摘要翻译：在MRAM器件的方法中，第一和第二图案在第二方向上交替且重复地形成在衬底上。每个第一图案和每个第二图案沿垂直于第二方向的第一方向延伸。去除一些第二图案以形成沿第一方向延伸的第一开口。形成填充第一开口的源极线。在第一和第二图案和源极线上形成掩模。掩模包括沿第一方向的第二开口，每个开口沿第二方向延伸。由第二开口暴露的第二图案的部分被去除以形成第三开口。形成填充第三开口的第三图案。由第一图案和第三图案包围的第二图案被去除以形成第四开口。形成填充第四开口的接触塞。

36. 发明申请

US20140264672A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20140264672A1
公开(公告)日：2014-09-18
申请号：US14182316
申请日：2014-02-18
申请人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
发明人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
IPC分类号： H01L27/22 , H01L43/12
CPC分类号： H01L27/228 , G11C11/161 , H01L43/12
摘要： In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.
摘要翻译：在MRAM器件的方法中，第一和第二图案在第二方向上交替且重复地形成在衬底上。每个第一图案和每个第二图案沿垂直于第二方向的第一方向延伸。去除一些第二图案以形成沿第一方向延伸的第一开口。形成填充第一开口的源极线。在第一和第二图案和源极线上形成掩模。掩模包括沿第一方向的第二开口，每个开口沿第二方向延伸。由第二开口暴露的第二图案的部分被去除以形成第三开口。形成填充第三开口的第三图案。由第一图案和第三图案包围的第二图案被去除以形成第四开口。形成填充第四开口的接触塞。

37. 发明申请

US20130011989A1 METHODS OF MANUFACTURING A DRAM DEVICE 失效
标题翻译：制造DRAM器件的方法
公开(公告)号：US20130011989A1
公开(公告)日：2013-01-10
申请号：US13540996
申请日：2012-07-03
申请人： Jong-Chul Park , Sang-Sup Jeong
发明人： Jong-Chul Park , Sang-Sup Jeong
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855 , H01L27/10876
摘要： In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.
摘要翻译：在制造DRAM器件的方法中，在衬底中形成掩埋型栅极。掩埋型栅极上形成封盖绝缘层图案。形成填充封盖绝缘层图案的部分之间的间隙的导电层图案，以及覆盖导电层图案和封盖绝缘层图案的绝缘夹层。蚀刻绝缘中间层，导电层图案，封盖绝缘层图案和基板的上部以形成开口，以及与第一焊盘区域接触的第一焊盘电极。间隔件形成在对应于第二垫区域的开口的侧壁上。第二焊盘电极形成在开口中。形成与第二焊盘电极电连接的位线和与第一焊盘电极电连接的电容器。

38. 发明授权

US07886063B2 User equipment, method and system for simultaneous session control 有权
标题翻译：用于同时进行会话控制的用户设备，方法和系统
公开(公告)号：US07886063B2
公开(公告)日：2011-02-08
申请号：US12353220
申请日：2009-01-13
申请人： Kang-Suk Huh , Young-Hwan Park , Chan Seok Lim , Jong-Chul Park , Young-Ae Kim
发明人： Kang-Suk Huh , Young-Hwan Park , Chan Seok Lim , Jong-Chul Park , Young-Ae Kim
IPC分类号： G06F15/16 , H04B1/38
CPC分类号： H04L65/4061 , H04L65/1006 , H04L65/1016 , H04L67/14 , H04W28/18 , H04W80/00 , H04W88/06
摘要： A user equipment (UE), method and system for processing session based communications, are discussed. According to an embodiment, the method includes receiving a message from a terminal that informs whether the terminal supports simultaneous PT (push-to) sessions; recognizing that the terminal supports simultaneous PT sessions according to the received message; and transporting data to one or more terminals through the server operating in B2BUA (Back-to-Back User Agent) mode, wherein a simultaneous PT session refers to a session where the server performs a PT session priority function or a PT session locking function.
摘要翻译：讨论了用于处理基于会话的通信的用户设备（UE），方法和系统。根据实施例，该方法包括：从终端接收消息，通知终端是否同时支持PT（推送）会话; 识别终端根据收到的消息支持PT会话; 并且通过B2BUA（背靠背用户代理）模式运行的服务器将数据传送到一个或多个终端，其中同时PT会话是指服务器执行PT会话优先级功能或PT会话锁定功能的会话。

39. 发明申请

US20100169812A1 Apparatus and method for providing widget service in portable terminal 审中-公开
标题翻译：在便携式终端中提供小部件服务的装置和方法
公开(公告)号：US20100169812A1
公开(公告)日：2010-07-01
申请号：US12655386
申请日：2009-12-30
申请人： Jong-Chul Park
发明人： Jong-Chul Park
IPC分类号： G06F3/048 , G06F9/44
CPC分类号： G06F21/54
摘要： A portable terminal includes an apparatus for enhancing security by preventing the control on an internal function of the portable terminal via a widget downloaded from a sharing site. The apparatus includes a widget engine for determining, when a widget in operation controls an internal function of the terminal, whether the widget is authorized to control the internal function, permitting the internal function control to the widget authorized to control the internal function, and blocking a widget prohibited from controlling the internal function, from controlling the internal function.
摘要翻译：便携式终端包括通过防止从共享站点下载的小部件来防止对便携式终端的内部功能的控制来增强安全性的装置。该装置包括一个小部件引擎，用于确定当操作的小部件控制终端的内部功能时，该小部件是否被授权控制内部功能，允许内部功能控制到被授权控制内部功能的小部件，以及阻止禁止控制内部功能的小部件，控制内部功能。

40. 发明申请

US20090285009A1 Nonvolatile memory devices using variable resistive elements 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20090285009A1
公开(公告)日：2009-11-19
申请号：US12453529
申请日：2009-05-14
申请人： Ki-Sung Kim , Byung-Gil Choi , Young-Ran Kim , Jong-Chul Park
发明人： Ki-Sung Kim , Byung-Gil Choi , Young-Ran Kim , Jong-Chul Park
IPC分类号： G11C11/00 , G11C7/00 , G11C5/14
CPC分类号： G11C13/0023 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2213/72
摘要： A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory cells. Local bit lines may be coupled with each row of the nonvolatile memory cells. Global bit lines may be selectively coupled with the multiple local bit lines.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件。非易失性存储器件可以包括存储单元阵列，其包括具有取决于存储的数据的可变电阻等级的多个非易失性存储单元的阵列。字线可以与非易失性存储单元的每一列耦合。局部位线可以与非易失性存储器单元的每一行耦合。全局位线可以选择性地与多个局部位线耦合。

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