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31. 发明授权

US6084817A Semiconductor memory with transfer buffer structure 有权
标题翻译：半导体存储器具有传输缓冲结构
公开(公告)号：US6084817A
公开(公告)日：2000-07-04
申请号：US264928
申请日：1999-03-09
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C5/02 , G11C7/10 , G11C8/00
CPC分类号： G11C5/025 , G11C7/10
摘要： A plurality of sense amplifiers are provided between a plurality of memory cell arrays having a plurality of memory cells. These sense amplifiers are connected to bit lines of the respective memory cell arrays by array selection switches. Each of the sense amplifiers is connected to data lines by column switches. An array control portion is provided at each of the memory cell arrays. This array control portion selectively controls the array selection switches and column switches to transmit the data in an arbitrary memory cell in a memory cell array to the data lines through the sense amplifier.
摘要翻译：在具有多个存储单元的多个存储单元阵列之间提供多个读出放大器。这些读出放大器通过阵列选择开关连接到各个存储单元阵列的位线。每个读出放大器通过列开关连接到数据线。在每个存储单元阵列中设置阵列控制部分。该阵列控制部分选择性地控制阵列选择开关和列开关，以通过读出放大器将存储单元阵列中的任意存储单元中的数据传输到数据线。

32. 发明授权

US5995442A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5995442A
公开(公告)日：1999-11-30
申请号：US236832
申请日：1999-01-25
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/04 , G11C11/407 , G11C11/41 , G11C11/413 , H01L27/10 , G06F13/16
CPC分类号： G11C7/1072 , G11C7/1018 , G11C7/22
摘要： A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.
摘要翻译：半导体存储器件包括存储单元组，所述存储单元组包括排列成矩阵的多个存储器单元; 指定电路，用于依次指定存储器单元中由连续地址寻址的存储器单元，并将其输入激活状态; 用于对由指定电路指定的连续存储单元进行数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路，该控制基于读出/ 从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得存储器对存储单元组的访问操作进行控制。

33. 发明授权

US5986949A Clock control circuit 有权
公开(公告)号：US5986949A
公开(公告)日：1999-11-16
申请号：US182691
申请日：1998-10-29
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G06F1/10 , G06F13/42 , G11C7/22 , G11C19/00 , H03K5/135 , H03L7/00 , G11C7/00
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： An external clock signal CK is input to a buffer, which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit which has a delay time of D2. The delay circuit generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units, each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2.times..DELTA..

34. 发明授权

US5949260A Clock signal processing circuit and semiconductor device in which a clock signal is processed in improved method 失效
标题翻译：时钟信号处理电路和其中以改进的方法处理时钟信号的半导体器件
公开(公告)号：US5949260A
公开(公告)日：1999-09-07
申请号：US887321
申请日：1997-07-02
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G06F1/10 , G11C7/00 , G11C7/22 , G11C11/401 , G11C11/4076 , H03K5/00 , H03K5/13 , H03L7/081 , H03L7/089
CPC分类号： G06F1/10 , G11C7/22 , H03K5/13 , H03L7/0812 , H03L7/089 , H03K2005/00026 , H03K2005/00195
摘要： A semiconductor device for inputting/outputting data in synchronism with a reference clock signal and an internal clock signal in each circuit. In this device, a variably delay section delays a generated clock signal to output an internal clock signal, and a phase error-detecting section detects a time difference between the internal clock signal and the reference clock signal, thereby controlling the delay amount of the variable delay section to make the time difference substantially zero.
摘要翻译：一种用于在每个电路中与参考时钟信号和内部时钟信号同步地输入/输出数据的半导体器件。在该装置中，可变延迟部延迟生成的时钟信号以输出内部时钟信号，相位误差检测部检测内部时钟信号与基准时钟信号之间的时间差，从而控制变量的延迟量延迟部分使时差基本为零。

35. 发明授权

US5943275A Semiconductor memory device 有权
公开(公告)号：US5943275A
公开(公告)日：1999-08-24
申请号：US181787
申请日：1998-10-28
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C29/04 , G11C7/00 , G11C11/401 , G11C11/407 , G11C29/00
CPC分类号： G11C29/785 , G11C29/808 , G11C29/846
摘要： It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.

36. 发明授权

US5818793A Clock-synchronous semiconductor memory device 失效
标题翻译：时钟同步半导体存储器件
公开(公告)号：US5818793A
公开(公告)日：1998-10-06
申请号：US457165
申请日：1995-06-01
申请人： Haruki Toda , Hitoshi Kuyama
发明人： Haruki Toda , Hitoshi Kuyama
IPC分类号： G11C7/10 , G11C8/04 , G11C7/00
CPC分类号： G11C8/04 , G11C7/1045 , G11C7/1072
摘要： A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O means is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.
摘要翻译：时钟同步半导体存储器件包括以矩阵形式布置的许多存储器单元，用于对连续的外部供给的基本时钟信号的实际循环次数进行计数的计数部分，用于输入行使能控制信号（/ RE）的控制部分，以及与基本时钟信号不同的外部设备提供的与基本控制信号同步的指令级别的列使能控制信号（/ CE），并且用于设置用于数据访问的初始地址以及用于执行由控制部分设置的地址的数据访问操作的数据I / O部分。在该设备中，通过控制部分设置初始地址之后并且在计数部分计数了指定数量的基本时钟信号之后，通过数据I / O装置从存储器单元输出数据。

37. 发明授权

US5708618A Multiport field memory 失效
标题翻译：多端口字段内存
公开(公告)号：US5708618A
公开(公告)日：1998-01-13
申请号：US658312
申请日：1996-06-05
申请人： Haruki Toda , Nobuo Watanabe
发明人： Haruki Toda , Nobuo Watanabe
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C8/16 , G11C11/41
CPC分类号： G11C7/10 , G11C7/1006 , G11C7/103 , G11C8/16
摘要： A multiport field memory includes cell arrays, bit line pairs, gate transmission circuits connecting to the bit line pairs, ports, and a data cross-transmission circuit. The data cross-transmission circuit has first and second transfer gate circuit pairs (each pair connected in series and each pair connected to each bit line pair). The ports, each includes a register for temporarily storing data and for transferring the data from or to the memory cell through the bit line pairs. Each port is connected to each bit line pair through each first and second transfer gate circuit pair. The data cross-transmission control circuit has the first and second transfer gate control circuit pairs to transfer first and second gate drive control signals in order to connect the bit line pair to the registers. The first transfer gate circuit in one pair of the first and second transfer gate circuit pairs is connected to the second transfer gate circuit in the same pair or another pair of the first and second transfer gate circuit pairs in order to transfer the data through a desired port under the control of the cross-transmission control circuit.
摘要翻译：多端口场存储器包括单元阵列，位线对，连接到位线对的栅极传输电路，端口和数据交叉传输电路。数据交叉传输电路具有第一和第二传输门电路对（每对串联连接，每对连接到每个位线对）。端口各自包括用于临时存储数据并通过位线对将数据从存储器单元传送到存储器单元的寄存器。每个端口通过每个第一和第二传输门电路对连接到每个位线对。数据交叉传输控制电路具有第一和第二传输门控制电路对以传送第一和第二栅极驱动控制信号，以将位线对连接到寄存器。一对第一和第二传输门电路对中的第一传输门电路连接到同一对或另一对第一和第二传输门电路对中的第二传输门电路，以便通过期望的端口在交叉传输控制电路的控制下。

38. 发明授权

US5706248A Data transfer system 失效
标题翻译：数据传输系统
公开(公告)号：US5706248A
公开(公告)日：1998-01-06
申请号：US751023
申请日：1996-11-15
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C7/10 , G11C8/04
CPC分类号： G11C7/1006 , G11C7/103
摘要： A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selecter circuit each arranged for k-unit group of the gates, for selecting the gates in unit of k-unit group; a plurality of data transfer paths for transferring data via the gates selected by the gate selecting means; a first register group composed of a-units of data registers for transferring data simultaneously to and from the data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting the data transfer paths connected to said designated data input/output gates with the data registers so that the data transfer paths connected to the designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (L.times.k) under the following conditions: if a (mod k).ident.0, 1, L=�a/k!+1 if other than the above, L=�a/k!+2 where L denotes a maximum number of the gate selecting means selectable simultaneously.
摘要翻译：一种数据传输系统，包括：以预定顺序由k-单元组以k-单元组排列的多个数据输入/输出门; 每个栅极选择器电路均设置用于k单元组的栅极，用于以k单元组为单位选择栅极; 用于经由门选择装置选择的门传送数据的多个数据传送路径; 由数据寄存器组成的第一寄存器组，用于同时传送数据传输路径和从数据传输路径传输数据，该单位数据寄存器以恒定顺序串行访问; 以及加扰电路，用于指定任何所需的数据输入/输出门，并且用于进一步选择性地将连接到所述指定的数据输入/输出门的数据传送路径与数据寄存器连接，使得连接到指定的输入/输出门的数据传送路径在以下条件下，当数据传输路径的数量为（Lxk）时，以预定的顺序连接到可串行访问的寄存器：如果（mod k）= 0,1，L = [a / k] + 1if 除了上述之外，L = [a / k] + 2其中L表示同时选择的选通选择装置的最大数目。

39. 发明授权

US5689473A Multi-bank synchronous memory system with cascade-type memory cell structure 失效
标题翻译：具有级联型存储单元结构的多行同步存储器系统
公开(公告)号：US5689473A
公开(公告)日：1997-11-18
申请号：US690479
申请日：1996-07-31
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/405 , G11C11/4091 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4045 , G11C11/4091 , G11C11/4096 , G11C7/1072
摘要： A synchronous memory system with a cascade-type memory cell structure has memory cells having a cascade type construction (or NAND type configuration), a row decoder, save registers, a sense amplifier, and a selector. The selector transmits a control signal to halt a sense operation for the memory cells when the sense operation for a target memory cell to be accessed in completed. The row decoder includes a decoder for decoding a row address, a latch circuit, a word line driver. The latch circuit stores a result of a decode operation, and the word line driver comprises a PMOS transistor and a NMOS transistor connected in series. A 8 volt power (Vpp) is supplied to the PMOS transistor in the word line driver.
摘要翻译：具有级联型存储单元结构的同步存储器系统具有具有级联类型结构（或NAND类型配置），行解码器，存储寄存器，读出放大器和选择器的存储器单元。当完成要访问的目标存储器单元的感测操作时，选择器发送控制信号以停止对存储器单元的感测操作。行解码器包括用于解码行地址的解码器，锁存电路，字线驱动器。锁存电路存储解码操作的结果，字线驱动器包括串联连接的PMOS晶体管和NMOS晶体管。 8 V功率（Vpp）被提供给字线驱动器中的PMOS晶体管。

40. 发明授权

US5612925A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5612925A
公开(公告)日：1997-03-18
申请号：US463394
申请日：1995-06-05
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/04 , G11C11/407 , G11C11/41 , G11C11/413 , H01L27/10
CPC分类号： G11C7/1072 , G11C7/1018 , G11C7/22
摘要： A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data beginning after a number of clock cycles (N) of the clock signal (N being a positive integer .gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.
摘要翻译：一种半导体存储器件，包括具有以行和列排列的多个存储单元的存储单元阵列，存储单元存储数据并根据地址信号进行选择。该装置包括控制单元，该控制单元接收时钟信号和用于在第一控制信号被断言之后与时钟信号同步地输出多个数据的第一控制或触发信号。在第一控制信号被断言之后的时钟信号（N为正整数> / = 2）的多个时钟周期（N）之后开始的数据的输出，在每个在输出开始直到输出多个数据之后的时钟周期。

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