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31. 发明授权

US6144599A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6144599A
公开(公告)日：2000-11-07
申请号：US191414
申请日：1998-11-12
申请人： Hironobu Akita , Kenji Tsuchida
发明人： Hironobu Akita , Kenji Tsuchida
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C29/00 , G11C29/04 , G11C11/419
CPC分类号： G11C7/06 , G11C11/4091 , G11C11/4094 , G11C7/12 , G11C29/83
摘要： In a DRAM semiconductor device comprising a bit line equalizer for setting a potential on paired bit lines to a potential on a precharge power source line, a sense amplifier circuit amplifying a potential difference across the paired bit lines and detecting data, sense amplifier drive lines, for applying a sense amplifier drive signal for driving the sense amplifier circuit to the sense amplifier circuit, and a sense amplifier/drive line equalizer, a current limiter element is so provided that, between a precharge power source line and the sense amplifier drive line, it is connected in series with the current path of the equalizer. By so providing the current limiter element, it is possible to, even if there occurs any cross-fail between the bit line and the word line, reduce a short-circuiting current at a precharging time or prevent generation of the short-circuiting current.
摘要翻译：在包括用于将成对位线上的电位设置为预充电电源线上的电位的位线均衡器的DRAM半导体器件中，放大成对位线之间的电位差和检测数据，读出放大器驱动线的读出放大器电路，为了将读出放大器驱动信号用于驱动读出放大器电路到读出放大器电路，以及读出放大器/驱动线均衡器，限流元件被设置成在预充电电源线和读出放大器驱动线之间，它与均衡器的当前路径串联连接。通过提供电流限制器元件，即使在位线和字线之间发生任何交叉故障，也可以在预充电时间减少短路电流或者防止短路电流的产生。

32. 发明授权

US08363771B2 Transmission device, receiving device and communication system 有权
标题翻译：传输设备，接收设备和通信系统
公开(公告)号：US08363771B2
公开(公告)日：2013-01-29
申请号：US12808598
申请日：2009-10-27
申请人： Hironobu Akita , Seiichi Ozawa , Yohei Ishizone , Satoshi Miura
发明人： Hironobu Akita , Seiichi Ozawa , Yohei Ishizone , Satoshi Miura
IPC分类号： H04L7/04
CPC分类号： H04L7/10 , G09G5/008 , H03L7/095 , H04L7/033 , H04L7/046
摘要： Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.
摘要翻译：提供具有简单配置并能够可靠地执行改变的比特率的确认的传输设备，接收设备和通信系统。通信系统1向发送装置3发送串行数据信号Sdata，该串行数据信号Sdata在传输中的串行数据信号Sdata的比特率时，在时钟周期的恒定倍数的周期内被设置为恒定值设备2更改。接收到串行数据信号Sdata的接收装置3当确定串行数据信号Sdata在时钟的周期的恒定倍数的周期内是恒定值时，从发送装置2接收训练数据Tdata，并且进行以确认改变的比特率的处理。

33. 发明授权

US06560163B2 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06560163B2
公开(公告)日：2003-05-06
申请号：US10040479
申请日：2002-01-09
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

34. 发明授权

US06452833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06452833B2
公开(公告)日：2002-09-17
申请号：US09773606
申请日：2001-02-02
申请人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
发明人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
IPC分类号： G11C1124
CPC分类号： G11C7/12 , G11C11/4094
摘要： A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.
摘要翻译： BL激光电路包括第一电容器，每个电容器的一端连接到第一位线，第一位线是相应对的位线之一，并且在另一端共同连接，第二电容器的一端连接到一端第二位线，其是相应对中的另一个位线并且在另一端共同连接，第一驱动器电路具有用于连接到第一电容器的另一端的公共连接节点的第一信号的输出节点具有连接到第二电容器的另一端的公共连接节点的第二信号的输出节点的第二驱动电路和用作连接在第一信号的输出节点和输出节点之间的均衡电路的开关电路对于第二个信号。

35. 发明授权

US06373303B1 Sync signal generating circuit provided in semiconductor integrated circuit 有权
公开(公告)号：US06373303B1
公开(公告)日：2002-04-16
申请号：US09846286
申请日：2001-05-02
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H03L706
摘要： A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a first ramp-voltage generating circuit for outputting a first voltage whose potential level begins to rise at a time of transition of a level of the output of the comparator replica and stops rising at a predetermined timing, a second ramp-voltage generating circuit for outputting a second voltage whose potential level begins to rise after the rising of the potential level of the first voltage stops, a voltage comparator for comparing the first and second voltages and outputting an internal clock signal, a second I/O replica for delaying the internal clock signal with a delay time substantially equal to the delay time of the first I/O replica, and a phase comparator for comparing a phase of an output of the second I/O replica and a phase of an input to the first I/O replica. A delay time in the comparator replica is adjusted on the basis of an output from the phase comparator.

36. 发明授权

US06370057B1 Semiconductor memory device having plate lines and precharge circuits 失效
标题翻译：具有板线和预充电电路的半导体存储器件
公开(公告)号：US06370057B1
公开(公告)日：2002-04-09
申请号：US09609774
申请日：2000-07-03
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： G11C1124
CPC分类号： H01L27/10897 , G11C7/12 , G11C11/4074 , G11C11/4094
摘要： A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines. Bit-line precharge circuits are provided at bit line pairs, respectively, to precharge and equalize the bit line pairs. An output potential of a plate potential generator is applied to the power supply terminals of the bit-line precharge circuits. The memory cells have a plurality of capacitors. A plate electrode of the capacitors are connected in common. An insulation film is formed on the plate electrode and a wiring layer is formed on the insulation film. The wiring layer is electrically connected to the plate electrode through a via hole formed in the insulation film and connected in common to the power supply terminals of the bit-line precharge circuits through a contact hole formed in the insulation film, thereby transmitting a potential in proportion to variations in plate potential.
摘要翻译：动态半导体存储器件包括各自具有单晶体管/单电容器的存储单元。存储单元被布置在位线和字线的各自交叉点处。分别在位线对上提供位线预充电电路，以对位线对进行预充电和均衡。板电位发生器的输出电位施加到位线预充电电路的电源端子。存储单元具有多个电容器。电容器的平板电极共同连接。在平板电极上形成绝缘膜，在绝缘膜上形成布线层。布线层通过形成在绝缘膜上的通孔与板电极电连接，并通过形成在绝缘膜上的接触孔共同连接到位线预充电电路的电源端，从而将电位传输到与板电位变化的比例。

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