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31. 发明授权

US08817325B2 Control device, image scanning apparatus, image forming apparatus, and method of controlling image scanning apparatus 有权
标题翻译：控制装置，图像扫描装置，图像形成装置以及图像扫描装置的控制方法
公开(公告)号：US08817325B2
公开(公告)日：2014-08-26
申请号：US12858843
申请日：2010-08-18
申请人： Sugitaka Oteki
发明人： Sugitaka Oteki
IPC分类号： H04N1/393 , G06T3/40
CPC分类号： H04N1/393 , H04N1/60
摘要： A control device including an image enlarging unit that creates enlarged image data of image data by repeatedly using a line in the image data; and a control unit that reads, from a storing unit in which the image data is stored, the image data and outputs, to the image enlarging unit, the image data for each line, the output being performed at time intervals corresponding to the number of times the line is used in accordance with an enlargement ratio of the image data to the enlarged image data.
摘要翻译：一种控制装置，包括：图像放大单元，通过重复使用图像数据中的一行来创建图像数据的放大图像数据; 以及控制单元，其从存储有图像数据的存储单元读取图像数据，并且将每行的图像数据输出到图像放大单元，该输出以对应于该数量的图像数据的时间间隔执行根据图像数据与放大图像数据的放大比率来使用线。

32. 发明授权

US07911647B2 Reader apparatus 有权
标题翻译：读卡器
公开(公告)号：US07911647B2
公开(公告)日：2011-03-22
申请号：US12121853
申请日：2008-05-16
申请人： Sugitaka Oteki
发明人： Sugitaka Oteki
IPC分类号： H04N1/00 , H04N1/40 , H04N1/46 , G06K9/36
CPC分类号： H04N1/40
摘要： A reader apparatus is provided that includes a reading part configured to read the image of an original material; a coding part configured to code the data of the read image; an image memory configured to contain the coded image data; and a controller configured to control the image reading and the image data coding. The coding part includes a part configured to count the number of lines of the image indicating its size in the original material feed direction; a part configured to code the image data with a provisional number of lines in response to the image size in the original material feed direction being unknown; and a part configured to determine the number of lines at the end of the image reading. The controller includes a part configured to replace the provisional number of lines in the coded data with the determined number of lines.
摘要翻译：提供一种阅读器装置，其包括被配置为读取原始图像的读取部件; 编码部，被配置为对所读取的图像的数据进行编码; 被配置为包含编码图像数据的图像存储器; 以及控制器，被配置为控制图像读取和图像数据编码。编码部分包括被配置为对表示其在原始材料馈送方向上的尺寸的图像的行数进行计数的部分; 响应于原料供给方向上的图像尺寸，配置成以临时数量的行编码图像数据的部件是未知的; 以及被配置为确定图像读取结束时的行数的部分。控制器包括被配置为用确定的行数替换编码数据中的临时行数的部分。

33. 发明授权

US5630023A Signal processor 失效
标题翻译：信号处理器
公开(公告)号：US5630023A
公开(公告)日：1997-05-13
申请号：US322498
申请日：1994-10-14
申请人： Sugitaka Oteki
发明人： Sugitaka Oteki
IPC分类号： G06G7/60 , G06F7/68 , G06F15/18 , G06F17/10 , G06N3/04 , G06N3/063
CPC分类号： G06F17/10 , G06F7/68 , G06N3/049 , G06N3/063
摘要： A signal processor comprises a first shift register delaying an output from a neuron-simulated element by m cycles, a second shift register delaying an output from a neuron-simulated element by n cycles, wherein n is different from m, a logical product circuit for computing two logical products of the outputs from the shift registers, and a circuit for computing an error signal according to a teacher signal and the two logical products.
摘要翻译：信号处理器包括将来自神经元仿真元件的输出延迟m个周期的第一移位寄存器，将来自神经元仿真元件的输出延迟n个周期的第二移位寄存器，其中n与m不同，逻辑积电路计算来自移位寄存器的输出的两个逻辑积，以及用于根据教师信号和两个逻辑积计算误差信号的电路。

34. 发明授权

US5485548A Signal processing apparatus using a hierarchical neural network 失效
标题翻译：信号处理装置采用分层神经网络
公开(公告)号：US5485548A
公开(公告)日：1996-01-16
申请号：US99719
申请日：1993-07-29
申请人： Sugitaka Oteki , Atsuo Hashimoto
发明人： Sugitaka Oteki , Atsuo Hashimoto
IPC分类号： G06N3/04 , G06N3/063 , G06F15/18
CPC分类号： G06N3/063 , G06N3/049
摘要： In a neural network configured of neuron model cells, each neuron model cell is adapted to hold an input signal when a forward process is performed and to hold an error signal inputted when a learning process is performed. The signal processing apparatus is arranged to execute the forward process and the learning process in parallel.
摘要翻译：在由神经元模型单元配置的神经网络中，当执行前向处理时，每个神经元模型单元适于保持输入信号，并且在执行学习处理时保持输入的误差信号。信号处理装置被配置为并行地执行前向处理和学习处理。

35. 发明授权

US5324991A Neuron unit and neuron unit network 失效
标题翻译：神经元单位和神经元单位网络
公开(公告)号：US5324991A
公开(公告)日：1994-06-28
申请号：US989605
申请日：1992-12-11
申请人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Atsuo Hashimoto , Sugitaka Oteki , Toshihiro Tsukagoshi , Satoshi Otsuki , Eiki Aono , Shuji Motomura , Takahiro Watanabe
发明人： Toshiyuki Furuta , Hiroyuki Horiguchi , Hirotoshi Eguchi , Atsuo Hashimoto , Sugitaka Oteki , Toshihiro Tsukagoshi , Satoshi Otsuki , Eiki Aono , Shuji Motomura , Takahiro Watanabe
IPC分类号： G06N3/063 , G06F15/18
CPC分类号： G06N3/063
摘要： A neuron unit processes a plurality of binary input signals and outputs a neuron output signal which is indicative of a result of the processing. The neuron unit is provided with a plurality of first gates respectively for carrying out a logical operation on a binary input signal and a weighting coefficient, a second gate for carrying out a logical operation on an excitatory output signal of each of the first gates, a third gate for carrying out a logic operation on an inhibitory output signal of each of the first gates, a fourth gate for synthesizing output signals of the second and third gates and outputting the neuron output signal, and a generating circuit for generating the weighting coefficients which are supplied to each of the first gates. The generating circuit for generating one weighting coefficient includes a random number generator for generating random numbers, and a comparator for comparing each random number r with a predetermined value q and for outputting a pulse signal having first and second values depending on whether each random number r is such that r.ltoreq.q or r>q, and each weighting coefficient is described by a pulse density.
摘要翻译：神经元单元处理多个二进制输入信号并输出指示处理结果的神经元输出信号。神经元单元分别设置有多个第一门，用于对二进制输入信号和加权系数进行逻辑运算，第二门用于对每个第一门的兴奋性输出信号进行逻辑运算，第三门，用于对每个第一门的抑制输出信号进行逻辑运算，第四门，用于合成第二和第三门的输出信号并输出神经元输出信号;以及产生电路，用于产生加权系数，被提供给每个第一门。用于产生一个加权系数的产生电路包括用于产生随机数的随机数发生器和用于将每个随机数r与预定值q进行比较的比较器，并且用于根据每个随机数r是否输出具有第一和第二值的脉冲信号是这样的，r = q或r> q，并且每个加权系数由脉冲密度来描述。

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