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31. 发明授权

US08354864B2 Sense amplifier for low voltage high speed sensing 有权
公开(公告)号：US08354864B2
公开(公告)日：2013-01-15
申请号：US13286166
申请日：2011-10-31
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

32. 发明申请

US20110121863A1 SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US20110121863A1
公开(公告)日：2011-05-26
申请号：US12972974
申请日：2010-12-20
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G11C7/08 , H03F3/45 , G11C7/06
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

33. 发明申请

US20080224774A1 Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation 有权
标题翻译：用于多级闪存操作的系统和随机变化和不匹配补偿的方法和装置
公开(公告)号：US20080224774A1
公开(公告)日：2008-09-18
申请号：US12131008
申请日：2008-05-30
申请人： Hieu Van Tran , Hung Quoc Nguyen
发明人： Hieu Van Tran , Hung Quoc Nguyen
IPC分类号： H03F3/45
CPC分类号： G11C16/28 , G11C7/02 , G11C7/062 , G11C7/08 , G11C11/5642 , G11C16/30
摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
摘要翻译：公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。对于NMOS感测晶体管，使用三重阱作为可变体电压。包括各种偏移补偿的差分放大器。有意义的意图偏移创建也包括在内。

34. 发明申请

US20140140138A1 Three-Dimensional Flash Memory System 有权
标题翻译：三维闪存系统
公开(公告)号：US20140140138A1
公开(公告)日：2014-05-22
申请号：US13680719
申请日：2012-11-19
申请人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
发明人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
IPC分类号： G11C16/06
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了三维闪存系统。

35. 发明申请

US20130242672A1 Non-volatile Memory Device And A Method Of Operating Same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20130242672A1
公开(公告)日：2013-09-19
申请号：US13419269
申请日：2012-03-13
申请人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
发明人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0425 , G11C16/06 , G11C16/12 , G11C16/30 , G11C16/3418
摘要： An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.
摘要翻译：在第一导电类型的半导体衬底中的非易失性存储单元阵列。每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。耦合栅极覆盖浮栅。擦除门覆盖第二区域。位线连接到第一区域。负电荷泵电路产生负电压。控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

36. 发明授权

US07616028B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US07616028B2
公开(公告)日：2009-11-10
申请号：US11942665
申请日：2007-11-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

37. 发明申请

US20110018634A1 Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation 审中-公开
标题翻译：用于多级闪存操作的系统和随机变化和不匹配补偿的方法和装置
公开(公告)号：US20110018634A1
公开(公告)日：2011-01-27
申请号：US12896783
申请日：2010-10-01
申请人： Hieu Van Tran , Hung Quoc Nguyen
发明人： Hieu Van Tran , Hung Quoc Nguyen
IPC分类号： H03F3/45
CPC分类号： G11C16/28 , G11C7/02 , G11C7/062 , G11C7/08 , G11C11/5642 , G11C16/30
摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
摘要翻译：公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。对于NMOS感测晶体管，使用三重阱作为可变体电压。包括各种偏移补偿的差分放大器。有意义的意图偏移创建也包括在内。

38. 发明授权

US07825698B2 Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation 有权
标题翻译：用于多级闪存操作的系统和随机变化和失配补偿的方法和装置
公开(公告)号：US07825698B2
公开(公告)日：2010-11-02
申请号：US12131008
申请日：2008-05-30
申请人： Hieu Van Tran , Hung Quoc Nguyen
发明人： Hieu Van Tran , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C16/28 , G11C7/02 , G11C7/062 , G11C7/08 , G11C11/5642 , G11C16/30
摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
摘要翻译：公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。对于NMOS感测晶体管，使用三重阱作为可变体电压。包括各种偏移补偿的差分放大器。有意义的意图偏移创建也包括在内。

39. 发明申请

US20100001765A1 SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US20100001765A1
公开(公告)日：2010-01-07
申请号：US12493240
申请日：2009-06-28
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： H03F3/45 , G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

40. 发明授权

US08049535B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US08049535B2
公开(公告)日：2011-11-01
申请号：US12972974
申请日：2010-12-20
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

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