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31. 发明申请

US20070007797A1 Vehicle water drainage structure 有权
标题翻译：车辆排水结构
公开(公告)号：US20070007797A1
公开(公告)日：2007-01-11
申请号：US11480550
申请日：2006-07-05
申请人： Hiroshi Seki
发明人： Hiroshi Seki
IPC分类号： B60R27/00
CPC分类号： B60H1/3233
摘要： A water drainage structure is provided to prevent drainage water from getting on hot components inside the engine compartment and suppress the occurrence of evaporation noise. At least one water drainage opening is provided in a bottom portion of a vehicle member arranged on the under surface of a floor panel of a vehicle. The downstream end portion of a water drainage pipe is arranged to communicate with the inside of a closed cross sectional structure formed by the floor panel and the vehicle member. Drainage water from a vehicle device flows out of the downstream end portion of the water drainage pipe and is discharged to the outside of the vehicle through the water drainage openings of the vehicle member. As a result, the drainage water is prevented from getting on hot components inside the engine compartment of the vehicle and the occurrence of evaporation noise is suppressed.
摘要翻译：提供排水结构，以防止排水从发动机舱内的热部件上排出，并抑制蒸发噪音的发生。至少一个排水口设置在布置在车辆底板的下表面上的车辆构件的底部中。排水管的下游端部布置成与由地板镶板和车辆构件形成的封闭横截面结构的内部连通。来自车辆装置的排水从排水管的下游端部流出，并通过车辆部件的排水口排出到车辆的外部。结果，能够防止排水在车内的发动机室内发热，能够抑制蒸发噪音的发生。

32. 发明授权

US07126859B2 Semiconductor integrated circuit that handles the input/output of a signal with an external circuit 有权
标题翻译：用于处理具有外部电路的信号的输入/输出的半导体集成电路
公开(公告)号：US07126859B2
公开(公告)日：2006-10-24
申请号：US10853007
申请日：2004-05-25
申请人： Hiroshi Seki
发明人： Hiroshi Seki
IPC分类号： G11C16/04
CPC分类号： H01L27/092 , H03K19/00315
摘要： A semiconductor integrated circuit that handles the input/output of a signal with an external circuit. The circuit includes a transistor transmitting a signal between the external circuit and an internal circuit with a drain/source therebetween at a given gate voltage. A first gate voltage supply circuit supplies a voltage at the gate of the transistor when supplied with a first power voltage at a first level of a control signal. A second gate voltage supply circuit supplies a voltage at the gate of the transistor when supplied with a second power voltage that is lower than the first power voltage at a second level of a control signal.
摘要翻译：一种用外部电路处理信号的输入/输出的半导体集成电路。电路包括在给定的栅极电压下在外部电路和内部电路之间传输信号的晶体管，其中漏极/源极之间的信号。第一栅极电压供应电路在被提供有控制信号的第一电平的第一电源电压时，提供在晶体管的栅极处的电压。第二栅极电压供应电路在被提供具有低于控制信号的第二电平处的第一电源电压的第二电源电压时，在晶体管的栅极处提供电压。

33. 发明授权

US06861724B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06861724B2
公开(公告)日：2005-03-01
申请号：US10647529
申请日：2003-08-26
申请人： Hiroshi Seki
发明人： Hiroshi Seki
IPC分类号： H01L27/04 , H01L21/822 , H03K17/687 , H03K19/00 , H03K19/0175 , H03K19/0185 , H01L29/00
CPC分类号： H03K19/018521
摘要： The invention provides an integrated circuit that permits input of a signal of a potential which is higher than a power supply voltage supplied to an interface circuit and also higher than a maximum rated voltage allowable for a gate electrode of a transistor forming an interface circuit, even in a non-access mode. The invention can include a gate voltage control circuit that produces a gate voltage to be applied to a gate electrode of a transfer gate which is connected between an external input terminal and an input end of an input buffer and transmits an external signal input from the external input terminal to the input end of the input buffer. The gate voltage control circuit outputs, as the gate voltage, a voltage produced based on a relatively high first voltage to be applied as a power supply voltage of a semiconductor integrated circuit in the access mode while outputting, as the gate voltage, a voltage produced based on a relatively low second voltage to be applied as a power supply voltage of the semiconductor integrated circuit in the non-access mode.
摘要翻译：本发明提供了一种集成电路，其允许输入高于提供给接口电路的电源电压的电位信号，并且还高于形成接口电路的晶体管的栅电极允许的最大额定电压，甚至处于非访问模式。本发明可以包括栅极电压控制电路，其产生要施加到传输门的栅电极的栅极电压，栅极电压连接在外部输入端子和输入缓冲器的输入端之间，并且传输从外部输入的外部信号输入端到输入缓冲器的输入端。栅极电压控制电路作为栅极电压输出基于要作为半导体集成电路的电源电压施加的相对高的第一电压产生的电压，作为栅极电压，作为栅极电压产生电压基于作为非接入模式中的半导体集成电路的电源电压施加的相对低的第二电压。

34. 发明授权

US06703650B2 Semiconductor integrated circuit including a circuit protecting against static electricity 有权
标题翻译：半导体集成电路包括保护静电的电路
公开(公告)号：US06703650B2
公开(公告)日：2004-03-09
申请号：US09885003
申请日：2001-06-21
申请人： Satoshi Ito , Hiroshi Seki
发明人： Satoshi Ito , Hiroshi Seki
IPC分类号： H01L2710
CPC分类号： H01L27/0255
摘要： When static electricity having an excessive voltage is applied to a VSS terminal, the static electricity may be transmitted to an inner cell directly connected to a VSS cell before the static electricity is discharged to the outside via an electrostatic protection circuit, possibly resulting in electrostatic destruction. Bypasses are thus provided to bypass the static electricity applied to a VSS terminal to a higher wiring layer, which allow only excessive static electricity to be selectively discharged to the outside via an electrostatic protection circuit.
摘要翻译：当施加过电压的静电施加到VSS端子时，静电可以在静电通过静电保护电路向外部排出之前传输到与VSS电池直接连接的内电池，可能导致静电破坏。因此提供了旁路，以将施加到VSS端子的静电旁路到较高的布线层，这允许仅通过静电保护电路将过多的静电选择性地放电到外部。

35. 发明授权

US06256875B1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06256875B1
公开(公告)日：2001-07-10
申请号：US09400912
申请日：1999-09-22
申请人： Masaki Watanabe , Akiyoshi Sawai , Yoshikazu Narutaki , Tomoaki Hashimoto , Masatoshi Yasunaga , Jun Shibata , Hiroshi Seki , Kazuhiko Kurafuchi , Katsunori Asai
发明人： Masaki Watanabe , Akiyoshi Sawai , Yoshikazu Narutaki , Tomoaki Hashimoto , Masatoshi Yasunaga , Jun Shibata , Hiroshi Seki , Kazuhiko Kurafuchi , Katsunori Asai
IPC分类号： H05K336
CPC分类号： H01L24/49 , H01L21/4857 , H01L23/13 , H01L23/3675 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L24/48 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/16195 , H01L2924/181 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49144 , Y10T29/49165 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.
摘要翻译：设置在印刷电路板球栅阵列封装的印刷电路板上的布线之间的最小间距减小。接线层比现有技术更窄，因为它们不被电镀，并且因为在布线层上仅镀一个金属层。可以容易地形成较窄的布线层，导线之间的间隔较小。

36. 发明授权

US6005289A Package for semiconductor device laminated printed circuit boards 失效
标题翻译：半导体器件层压印刷电路板封装
公开(公告)号：US6005289A
公开(公告)日：1999-12-21
申请号：US738935
申请日：1996-10-24
申请人： Masaki Watanabe , Akiyoshi Sawai , Yoshikazu Narutaki , Tomoaki Hashimoto , Masatoshi Yasunaga , Jun Shibata , Hiroshi Seki , Kazuhiko Kurafuchi , Katsunori Asai
发明人： Masaki Watanabe , Akiyoshi Sawai , Yoshikazu Narutaki , Tomoaki Hashimoto , Masatoshi Yasunaga , Jun Shibata , Hiroshi Seki , Kazuhiko Kurafuchi , Katsunori Asai
IPC分类号： H05K3/46 , H01L21/48 , H01L23/12 , H01L23/13 , H01L23/367 , H01L23/498 , H01L23/053 , H01L23/48
CPC分类号： H01L24/49 , H01L21/4857 , H01L23/13 , H01L23/3675 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/16195 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49144 , Y10T29/49165
摘要： The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.
摘要翻译：设置在印刷电路板球栅阵列封装的印刷电路板上的布线之间的最小间距减小。接线层比现有技术更窄，因为它们不被电镀，并且因为在布线层上仅镀一个金属层。可以容易地形成较窄的布线层，导线之间的间隔较小。

37. 发明授权

US5128840A Bicycle luminaire 失效
标题翻译：自行车灯具
公开(公告)号：US5128840A
公开(公告)日：1992-07-07
申请号：US548862
申请日：1990-07-06
申请人： Hiroshi Seki , Kazunari Maeda
发明人： Hiroshi Seki , Kazunari Maeda
IPC分类号： B62J6/06 , H02K7/18
CPC分类号： B62J6/06 , H02K7/1846
摘要： A bicycle luminaire has first permanent magnets on spokes of a bicycle wheel, and a detection unit fixed to a stationary portion of the bicycle. The detection unit has a second permanent magnet, a Wiegand wire and a sensing coil. In place of the first magnets, Wiegand wires can be disposed on the spokes, and the detection unit can be formed with two magnets and sensing coil.
摘要翻译：自行车灯具在自行车车轮的轮辐上具有第一永磁体，并且固定在自行车的静止部分上的检测单元。检测单元具有第二永磁体，韦根线和感测线圈。代替第一个磁体，可以将Wiegand电线布置在辐条上，并且检测单元可以形成有两个磁体和感测线圈。

38. 发明授权

US4704370A Sealing glass composition 失效
标题翻译：密封玻璃组成
公开(公告)号：US4704370A
公开(公告)日：1987-11-03
申请号：US548448
申请日：1983-11-03
申请人： Hiroshi Seki , Toshiki Nishiyuki
发明人： Hiroshi Seki , Toshiki Nishiyuki
IPC分类号： C04B37/00 , C03C3/074 , C03C8/24 , C03C14/00 , C04B37/02 , C09J1/00 , H01L23/10
CPC分类号： H01L23/10 , C03C14/004 , C03C3/0745 , C03C8/24 , C03C2214/04 , H01L2924/0002 , H01L2924/09701
摘要： A sealing glass composition comprising from 75 to 50% by volume of low-melting glass powder containing PbO as the main component, from 20 to 45% by volume of ceramics powder having a thermal expansion coefficient of at most 30.times.10.sup.-7 .degree. C..sup.-1 in a range of from room temperature to 300.degree. C. and from 5 to 30% by volume of TiO.sub.2 -SnO.sub.2 solid solution powder.
摘要翻译：一种密封玻璃组合物，其包含75至50体积％的含有PbO作为主要成分的低熔点玻璃粉末，20至45体积％的热膨胀系数至多为30×10 -7℃的陶瓷粉末， 1在室温至300℃的范围内和5至30体积％的TiO 2 -SnO 2固溶体粉末。

39. 发明授权

US10360315B2 Construction field management method and construction field management device 有权
公开(公告)号：US10360315B2
公开(公告)日：2019-07-23
申请号：US14349247
申请日：2011-10-03
申请人： Hiroshi Seki , Satoshi Shimakura
发明人： Hiroshi Seki , Satoshi Shimakura
IPC分类号： G06F17/50 , G06Q50/08 , G06Q10/06 , G06Q10/10
摘要： The object is to enable easy acquisition of an element that is not design data. The technique is characterized in that when generating construction field management information used to manage a construction field, a construction field management device acquires measurement data that is three-dimensional shape data measured by a measurement device, and compares design data created by a designer with the acquired measurement data, thus extracting non-design data that is not the design data, from the measurement data. Also, as the non-design data, data of a scaffolding/tool and a component of the design data in a temporarily placed state are extracted, and the status of these is analyzed and displayed on a display unit.

40. 发明授权

US08253449B2 Clock switch circuit and clock switch method of the same 失效
标题翻译：时钟开关电路和时钟切换方法相同
公开(公告)号：US08253449B2
公开(公告)日：2012-08-28
申请号：US12787687
申请日：2010-05-26
申请人： Hiroshi Seki , Kiyoshi Kirino
发明人： Hiroshi Seki , Kiyoshi Kirino
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/667 , G06F1/08
摘要： A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values.
摘要翻译：时钟切换电路包括：分频电路，其分频基本时钟的频率以产生多个分频时钟;输出选择信号产生电路，其根据时钟选择信号输出输出选择信号;以及输出选择电路，其根据输出选择信号切换要输出的时钟，其中，分频电路从频率分配电路的每一个的一个周期的开始输出指示基本时钟的时钟数的多个分频计数值，并且输出选择信号发生电路在开关操作之前和之后的分频时钟的开始周期的开始定时基于对应于电流的分频计数值的定时处切换输出选择信号的值多个分频计数值中的选择时钟。

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