专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06772317B2 Method and apparatus for optimizing load memory accesses 失效
标题翻译：用于优化加载存储器访问的方法和装置
公开(公告)号：US06772317B2
公开(公告)日：2004-08-03
申请号：US09861050
申请日：2001-05-17
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
IPC分类号： G06F9312
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3832 , G06F9/384
摘要： A computer architecture to process load instructions by allowing multiple mappings between logical registers and the same physical register is disclosed. The computer architecture includes a processor having a physical registers. The processor also includes a decoder to decode a load instruction that names a destination logical register. The processor also includes a register allocation table to map the destination logical register to a physical register within the plurality of physical registers. If the load instruction is predicted to collide with a prior load instruction that names a destination logical register, then the register allocation table maps the destination logical register to the physical register allocated to the first load instruction.
摘要翻译：公开了通过允许逻辑寄存器和相同物理寄存器之间的多个映射来处理加载指令的计算机体系结构。计算机体系结构包括具有物理寄存器的处理器。处理器还包括解码器，用于解码命名目的地逻辑寄存器的加载指令。处理器还包括寄存器分配表，以将目的地逻辑寄存器映射到多个物理寄存器内的物理寄存器。如果预期加载指令与命名目的地逻辑寄存器的先前加载指令相冲突，则寄存器分配表将目的地逻辑寄存器映射到分配给第一加载指令的物理寄存器。

32. 发明授权

US06675280B2 Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher 有权
标题翻译：用于识别内容感知预取器中的候选虚拟地址的方法和装置
公开(公告)号：US06675280B2
公开(公告)日：2004-01-06
申请号：US10000549
申请日：2001-11-30
申请人： Robert N. Cooksey , Stephan J. Jourdan
发明人： Robert N. Cooksey , Stephan J. Jourdan
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0215 , G06F12/0862 , G06F2212/6028
摘要： A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.
摘要翻译：一种用于识别高速缓存线中的虚拟地址的方法和装置。为了区分候选虚拟地址与数据值和随机位模式，将高速缓存行中的地址大小的字的高位与高速缓存行的有效地址的高位进行比较。如果地址大小字的高位匹配有效地址的高位，那么将地址大小的字识别为候选虚拟地址。

33. 发明授权

US08850250B2 Integration of processor and input/output hub 有权
标题翻译：处理器和输入/输出集线器的集成
公开(公告)号：US08850250B2
公开(公告)日：2014-09-30
申请号：US12791836
申请日：2010-06-01
申请人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
发明人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
摘要翻译：描述了用于集成处理器和输入/输出集线器的方法和装置。在一个实施例中，边带信号可能导致处理器或集成I / O逻辑的电源管理状态的改变。单个集成电路管芯可以包括处理器和集成I / O逻辑。还公开了其他实施例。

34. 发明授权

US08291196B2 Forward-pass dead instruction identification and removal at run-time 失效
标题翻译：在运行时前进死亡指令识别和删除
公开(公告)号：US08291196B2
公开(公告)日：2012-10-16
申请号：US11323037
申请日：2005-12-29
申请人： Stephan J. Jourdan , Matthew C. Merten , Alexandre J. Farcy
发明人： Stephan J. Jourdan , Matthew C. Merten , Alexandre J. Farcy
IPC分类号： G06F9/00
CPC分类号： G06F9/3832 , G06F9/3838
摘要： Apparatuses and methods for dead instruction identification are disclosed. In one embodiment, an apparatus includes an instruction buffer and a dead instruction identifier. The instruction buffer is to store an instruction stream having a single entry point and a single exit point. The dead instruction identifier is to identify dead instructions based on a forward pass through the instruction stream.
摘要翻译：公开了用于死指示识别的装置和方法。在一个实施例中，一种装置包括指令缓冲器和死指令标识符。指令缓冲器用于存储具有单个入口点和单个出口点的指令流。死指令标识符是基于通过指令流的向前传递来识别死指令。

35. 发明授权

US07562206B2 Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions 有权
标题翻译：用于动态和静态预测指令资源利用率以生成执行集群分区的多级方案
公开(公告)号：US07562206B2
公开(公告)日：2009-07-14
申请号：US11323043
申请日：2005-12-30
申请人： Avinash Sodani , Alexandre J. Farcy , Stephan J. Jourdan , Per Hammarlund , Mark C. Davis
发明人： Avinash Sodani , Alexandre J. Farcy , Stephan J. Jourdan , Per Hammarlund , Mark C. Davis
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3012 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are decoded into micro-operations. Execution of one set of micro-operations is predicted to involve execution resources to perform memory access operations and inter-cluster communication, but not to perform branching operations. Execution of a second set of micro-operations is predicted to involve execution resources to perform branching operations but not to perform memory access operations. The micro-operations are partitioned for execution in accordance with these predictions, the first set of micro-operations to a first cluster of execution resources and the second set of micro-operations to a second cluster of execution resources. The first and second sets of micro-operations are executed out of sequential order and are retired to represent their sequential instruction ordering.
摘要翻译：公开了用于预测执行群集并促进群集间通信的微架构策略和结构。在所公开的实施例中，顺序排序的指令被解码成微操作。预计执行一组微操作涉及执行资源以执行存储器访问操作和集群间通信，但不执行分支操作。预计第二组微操作的执行涉及执行资源以执行分支操作，但不执行存储器访问操作。根据这些预测将微操作划分为执行，即第一组执行资源的第一组微操作和第二组执行资源的第二组微操作。第一组和第二组微操作按顺序执行，并退出以表示其顺序指令排序。

36. 发明授权

US07539850B2 Enhanced virtual renaming scheme and deadlock prevention therefor 失效
标题翻译：增强的虚拟重命名方案和防止死锁
公开(公告)号：US07539850B2
公开(公告)日：2009-05-26
申请号：US10351444
申请日：2003-01-27
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F9/34
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
摘要翻译：在处理器内的增强型虚拟重命名方案中，可以将多个逻辑寄存器映射到单个物理寄存器。值缓存确定根据程序指令生成的新值是否与先前执行的指令相关联的值匹配。如果是，则与新执行的指令相关联的逻辑寄存器共享物理寄存器。此外，死锁预防措施可以以在处理器核心中产生来自旧指令的值产生时从较小执行指令“窃取”物理寄存器的方式集成到寄存器分配单元中。

37. 发明授权

US07349284B2 Memory array with staged output 有权
标题翻译：具有分段输出的内存阵列
公开(公告)号：US07349284B2
公开(公告)日：2008-03-25
申请号：US11315160
申请日：2005-12-23
申请人： Stephan J. Jourdan , Boyd S. Phelps , Chris E. Yuker
发明人： Stephan J. Jourdan , Boyd S. Phelps , Chris E. Yuker
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C11/413
摘要： Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.
摘要翻译：本发明的实施例提供了一种用于将从可寻址存储器位置输出的数据分段为多个场的方法和系统。在实施例中，可以在不同的时钟周期期间输出存储在地址处的数据项的每个字段。在另外的实施例中，可以首先输出大多数时间关键字段。

38. 发明授权

US07155599B2 Method and apparatus for a register renaming structure 有权
标题翻译：一种寄存器重命名结构的方法和装置
公开(公告)号：US07155599B2
公开(公告)日：2006-12-26
申请号：US09750095
申请日：2000-12-29
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
IPC分类号： G06F9/40
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3857
摘要： A processor having a register renaming structure and method is disclosed to recover a free list. The processor includes a physical register file including physical registers. The processor also includes a decoder to decode an instruction to indicate a destination logical register. The processor also includes a register allocation table to map the destination logical register to an allocated physical register. The processor also includes an active list that includes an old field and a new field. The old field includes at least one evicted physical register from the register alias table. The new field includes the allocated physical register. The processor also includes the free list of unallocated physical registers reclaimed from the active list.
摘要翻译：公开了具有寄存器重命名结构和方法的处理器来恢复空闲列表。该处理器包括一个包括物理寄存器的物理寄存器文件。处理器还包括解码器，用于解码指示目的地逻辑寄存器的指令。处理器还包括寄存器分配表，以将目的地逻辑寄存器映射到所分配的物理寄存器。该处理器还包括一个包含旧字段和新字段的活动列表。旧字段至少包含一个从寄存器别名表中删除的物理寄存器。新的领域包括分配的物理寄存器。处理器还包括从活动列表中回收的未分配物理寄存器的空闲列表。

39. 发明授权

US07093077B2 Method and apparatus for next-line prefetching from a predicted memory address 有权
公开(公告)号：US07093077B2
公开(公告)日：2006-08-15
申请号：US10163977
申请日：2002-06-05
申请人： Robert N. Cooksey , Stephan J. Jourdan
发明人： Robert N. Cooksey , Stephan J. Jourdan
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F2212/6026 , G06F2212/6028
摘要： A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory address contiguous with the predicted memory address. Any subsequent next-line prefetch request corresponds to a cache line having a memory address contiguous with a memory address associated with a preceding next-line prefetch request.

40. 发明授权

US07080236B2 Updating stack pointer based on instruction bit indicator without executing an update microinstruction 失效
标题翻译：基于指令位指示器更新堆栈指针，而不执行更新微指令
公开(公告)号：US07080236B2
公开(公告)日：2006-07-18
申请号：US10262214
申请日：2002-09-30
申请人： Stephan J. Jourdan , Alan B. Kyker , Nicholas G. Samra
发明人： Stephan J. Jourdan , Alan B. Kyker , Nicholas G. Samra
IPC分类号： G06F9/312
CPC分类号： G06F9/38 , G06F9/30101
摘要： A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.
摘要翻译：一种堆栈指针更新技术，其中堆栈指针被更新而不执行微操作以添加或减去堆栈指针值。还描述了堆栈指针更新技术，以将堆栈指针重置为预定值，而不执行微操作以将堆栈指针值加或减。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式