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    • 31. 发明授权
    • Semiconductor device having power supply voltage routed through substrate
    • 具有通过衬底的电源电压的半导体器件
    • US06727578B1
    • 2004-04-27
    • US09392276
    • 1999-09-09
    • David B. ScottHeng-Chih Lin
    • David B. ScottHeng-Chih Lin
    • H01L2352
    • H01L27/0921H01L27/0203H01L2924/0002H01L2924/00
    • A semiconductor device (200) having a substrate routed power supply voltage is disclosed. The semiconductor device (200) includes a relatively highly doped substrate (302) and an epitaxial layer (304) formed over the substrate (302). In one embodiment (200), a surrounding conductive structure (202) is formed on the peripheral edges of the semiconductor device (200) die. The surrounding conductive structure (202) is coupled to the substrate (302). In another embodiment, the back side of the die (404) is coupled to the conductive portion (402) of an integrated circuit package. The conductive portion (402) is coupled to a power supply voltage. In another embodiment (700), the surrounding conductive structure (702) is coupled to a power supply voltage by one or more bond pads (710) formed on, or coupled to, the surrounding conductive structure (702).
    • 公开了具有基板路由电源电压的半导体器件(200)。 半导体器件(200)包括相对高掺杂的衬底(302)和形成在衬底(302)上的外延层(304)。 在一个实施例(200)中,在半导体器件(200)管芯的周边边缘上形成周围的导电结构(202)。 周围的导电结构(202)耦合到衬底(302)。 在另一个实施例中,管芯(404)的背面耦合到集成电路封装的导电部分(402)。 导电部分(402)耦合到电源电压。 在另一实施例(700)中,周围的导电结构(702)通过一个或多个在周围的导电结构(702)上形成或耦合到其上的接合焊盘(710)耦合到电源电压。
    • 32. 发明授权
    • Minimization and linearization of ESD parasitic capacitance in integrated circuits
    • 集成电路中ESD寄生电容的最小化和线性化
    • US06690066B1
    • 2004-02-10
    • US10274163
    • 2002-10-18
    • Heng-Chih LinCharvaka DuvvuryBaher Haroun
    • Heng-Chih LinCharvaka DuvvuryBaher Haroun
    • H01L2362
    • H01L27/0266
    • An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive sub-circuit 302, each sub-circuit including an MOS transistor. The circuit comprises a direct connection between the I/O pad 303 and the drain 321 of the drive sub-circuit MOS transistor 306, and further a forward diode 360 inserted between the I/O pad 303 and the drain 311 of the discharge sub-circuit MOS transistor 305 to isolate the junction capacitance of the discharge sub-circuit MOS transistor, whereby electrical noise coupling to the substrate is reduced, RF/analog input signals are improved, and leakage at the I/O pad is reduced.
    • 保护I / O焊盘303抵抗ESD脉冲的集成电路,该电路在同一衬底中具有放电子电路301和驱动子电路302,每个子电路包括MOS晶体管。 电路包括驱动子电路MOS晶体管306的I / O焊盘303和漏极321之间的直接连接,以及插入在放电子晶体管306的I / O焊盘303和漏极311之间的正二极管360。 电路MOS晶体管305隔离放电次电路MOS晶体管的结电容,由此降低耦合到衬底的电噪声,提高RF /模拟输入信号,并减小I / O焊盘的漏电。
    • 33. 发明授权
    • Electronic apparatus and clock generating method thereof
    • 电子设备及其时钟产生方法
    • US08531216B1
    • 2013-09-10
    • US13557172
    • 2012-07-24
    • Jin-Xiao WuHeng-Chih LinYi-Bin Hsieh
    • Jin-Xiao WuHeng-Chih LinYi-Bin Hsieh
    • H03L7/00
    • H03J7/04
    • The present invention discloses an electronic apparatus. The electronic apparatus comprises a reference oscillator, for generating a reference clock; a first communications module, comprising a first auto frequency control unit, for detecting a first frequency offset between the first communications module and a first communication device and generating a first detecting result; and a first frequency synthesizer, for adjusting the reference clock according to the first detecting result, to generate a first baseband clock; and a second communications module, comprising a second auto frequency control unit, for detecting a second frequency offset between the second communications module and a second communication device and generating a second detecting result; a second frequency synthesizer, for receiving and outputting the first baseband clock; and a compensation unit, for adjusting the first baseband clock according to the first detecting result and the second detecting result, to generate a second baseband clock.
    • 本发明公开了一种电子设备。 电子设备包括用于产生参考时钟的参考振荡器; 第一通信模块,包括第一自动频率控制单元,用于检测第一通信模块和第一通信设备之间的第一频率偏移并产生第一检测结果; 以及第一频率合成器,用于根据第一检测结果调整参考时钟,以产生第一基带时钟; 以及第二通信模块,包括第二自动频率控制单元,用于检测所述第二通信模块和第二通信设备之间的第二频率偏移并产生第二检测结果; 第二频率合成器,用于接收和输出第一基带时钟; 以及补偿单元,用于根据第一检测结果和第二检测结果调整第一基带时钟,以产生第二基带时钟。
    • 35. 发明申请
    • DYNAMIC BANDWIDTH COMPENSATING METHOD AND ASSOCIATED APPARATUS
    • 动态带宽补偿方法及相关设备
    • US20080157874A1
    • 2008-07-03
    • US11968296
    • 2008-01-02
    • Heng-Chih Lin
    • Heng-Chih Lin
    • H03G3/30
    • H03G5/24H03F1/083H03F3/45085H03F3/45183H03F3/45475H03F2200/153H03F2203/45512H03F2203/45514H03F2203/45522H03H11/126H03H11/1291
    • A programmable gain amplifier includes an operational amplifier coupled thereto a plurality of resistors to perform a feedback control, thereby rendering a closed-loop gain A f  ( s ) = A  ( s ) 1 + A  ( s ) · β , where β is a feedback factor determined by the resistance of the resistors and A(s) is an open-loop gain of the operational amplifier. The operational amplifier includes a first-stage amplifying circuit, a second-stage amplifying circuit, and a compensating capacitor coupled to an output end of the first-stage amplifying circuit and having an equivalent capacitance variable to adjust a dominant-pole frequency of the open-loop gain of the operational amplifier.
    • 可编程增益放大器包括与多个电阻耦合的运算放大器,以执行反馈控制,从而产生闭环增益,即:“MATH-US-00001”num =“00001”> s = MO> / MN> + A MI>
        • 36. 发明申请
        • High dynamic range pre-power amplifier incorporating digital attenuator
        • 包含数字衰减器的高动态范围前置功率放大器
        • US20070129030A1
        • 2007-06-07
        • US11296148
        • 2005-12-06
        • Petteri LitmanenHeng-Chih Lin
        • Petteri LitmanenHeng-Chih Lin
        • H04B1/04H01Q11/12
        • H03G1/0088H03F1/0205H03F1/0277H03F3/211H03F3/72H03F2200/331H03F2200/366H03F2203/21145H03G3/001H04B1/0483
        • A novel digital attenuator circuit and associated pre-power amplifier (PPA) that substantially increases the dynamic range of the amplifier. Increased dynamic range is achieved by placing a digital current attenuator circuit at the output of the pre-power amplifier so that the minimum possible current output of the transistor switch array of the PPA can be further attenuated. The attenuator functions to split the current between the load and the power supply VDD (i.e. AC ground) based on device ratio that is controlled digitally via an input power control word. The digital attenuator is constructed as a segmented digitally controlled matrix or cell array comprising at least a pass and bypass matrix or array. The pass matrix controls the amount of current output from the PPA while the bypass matrix controls the amount of current shorted to the AC ground (i.e. power supply). By varying the number of transistors on or off in each matrix, the power output of the PPA can be easily and accurately controlled.
        • 一种新颖的数字衰减器电路和相关的预功率放大器(PPA),其大大增加了放大器的动态范围。 通过将数字电流衰减器电路放置在预功率放大器的输出端,使得PPA的晶体管开关阵列的最小可能的电流输出可以被进一步衰减来实现增加的动态范围。 衰减器用于根据通过输入功率控制字以数字方式控制的器件比例,在负载和电源V DD(即交流地)之间分流电流。 数字衰减器被构造为包括至少一个通过和旁路矩阵或阵列的分段数字控制矩阵或单元阵列。 通过矩阵控制从PPA输出的电流量,而旁路矩阵控制短路到交流地(即电源)的电流量。 通过改变每个矩阵中的晶体管的数量,可以容易且准确地控制PPA的功率输出。
        • 37. 发明授权
        • Current switching arrangement for D.A.C. reconstruction filtering
        • 电流开关装置 重建过滤
        • US07098830B2
        • 2006-08-29
        • US10821576
        • 2004-04-09
        • Heng-Chih LinChien-Chung Chen
        • Heng-Chih LinChien-Chung Chen
        • H03M1/66H03M1/06H04B1/10
        • H03M1/0614H03M1/662H03M1/742
        • An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.
        • 一种布置提供了表示数字输入信号的值的减少谐波含量输出信号。 该装置包括多个存储装置301。 。 。 配置成在时钟信号的不同相位采样和存储数字输入信号。 该装置还具有多个电流转向数模转换器(DAC)311。 。 。 被配置为从多个存储设备中的相应存储设备接收相应的存储的数字信号,并且提供表示所接收的存储的数字信号的相应电流。 该装置还包括组合装置,其被配置为组合来自多个电流导向DAC中的相应电流的电流,以便提供表示数字输入信号的值的减少的谐波含量输出信号。
        • 39. 发明授权
        • Wide band, wide operation range, general purpose digital phase locked loop architecture
        • 宽带宽,操作范围广泛,通用数字锁相环架构
        • US06798296B2
        • 2004-09-28
        • US10292225
        • 2002-11-12
        • Heng-Chih LinBaher S. HarounTiang Tun Foo
        • Heng-Chih LinBaher S. HarounTiang Tun Foo
        • H03L700
        • H03K3/0322H03K5/1252H03L7/089H03L7/093H03L7/18H03L2207/50
        • A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.
        • 宽带,宽工作范围,通用数字锁相环(PLL)在数字域内运行,除了相关的时间数字转换器(T2D)和数字控制振荡器(DCO)外。 通过快速校准T2D和DCO,无论输入时钟频率,电源电压,处理和温度如何,通过使用校准的相位频率检测(PFD)和DCO信息来对控制回路校正进行归一化来实现恒定的PLL环路BW 变化。 PLL环路BW与操作条件和半导体器件变化完全解耦。 这意味着可以非常积极地选择PLL环路BW来抑制噪声,从而实现低抖动,高性能的PLL。 此外,由于该PLL可以在宽的工作范围内可靠地工作,所以它是一个单一设计的通用PLL。
        • 40. 发明授权
        • Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time
        • 无毛刺时钟多路复用电路,具有异步开关控制和最小开关时间
        • US06784699B2
        • 2004-08-31
        • US10292243
        • 2002-11-12
        • Baher S. HarounHeng-Chih LinTim Foo
        • Baher S. HarounHeng-Chih LinTim Foo
        • H03K1700
        • G06F1/08H03K3/0322H03K5/1252H03L7/093H03L7/18H03L2207/50
        • A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa. More importantly, the complete switch over only takes two cycles of the targeted clock in the best case once the active clock is turned off, when switching from slow to fast clock; and four target clock cycles in the worst case once the active clock is turned off, when switching from fast to slow clock.
        • 假设相应的时钟本身是稳定的,对称无毛刺时钟多路复用电路允许在操作期间的任何时刻将数字或模拟处理单元的输入时钟从一个频率切换到另一个频率。 时钟或开关控制信号不以任何方式同步的限制。 该电路保证无毛刺输出,并且还可以防止输出时钟的短暂循环。 由于所有相关时钟和开关控制信号都是异步的,因此该电路进一步消除了元稳定性问题。 其对称架构允许电路工作,输出时钟从慢时钟切换到快时钟,反之亦然。 更重要的是,一旦活动时钟关闭,当从慢速切换到快速时钟时,完全切换只需要两个周期的目标时钟; 在最坏情况下,一旦活动时钟关闭,当从快速切换到慢时钟时,则有四个目标时钟周期。