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31. 发明申请

US20080128805A1 SEMICONDUCTOR DEVICE WITH BLOCK LAYER AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：具有块层的半导体器件及其制造方法
公开(公告)号：US20080128805A1
公开(公告)日：2008-06-05
申请号：US11947429
申请日：2007-11-29
申请人： Haruhiko Koyama
发明人： Haruhiko Koyama
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0692 , H01L29/4238 , H01L29/7834
摘要： A semiconductor memory device includes a well layer having a first conductivity type and formed in a semiconductor substrate, a block layer formed in a trench and formed of an insulating layer, a gate electrode formed on the semiconductor substrate apart from the block layer, a first diffusion layer having a second conductivity type, formed on a surface of the semiconductor substrate, and having a high impurity concentration region to a first depth from the surface of the semiconductor substrate, a second diffusion layer having the second conductivity type, formed on the surface of the semiconductor substrate on a side of the block layer away from the gate electrode, having a high impurity concentration region to a second depth greater than the first depth from the surface of the semiconductor substrate, and electrically connected to the first diffusion layer, and a contact connected to the second diffusion layer.
摘要翻译：半导体存储器件包括具有第一导电类型并形成在半导体衬底中的阱层，形成在沟槽中并由绝缘层形成的阻挡层，形成在半导体衬底上的与阻挡层分开的栅电极，第一具有第二导电类型的扩散层，形成在半导体衬底的表面上，并且具有从半导体衬底的表面到第一深度的高杂质浓度区域，形成在表面上的具有第二导电类型的第二扩散层所述半导体衬底在所述阻挡层的远离所述栅电极的一侧上具有高的杂质浓度区域，其大于距所述半导体衬底的表面的所述第一深度的第二深度，并且电连接到所述第一扩散层，以及连接到第二扩散层的触点。

32. 发明申请

US20070077719A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20070077719A1
公开(公告)日：2007-04-05
申请号：US11536291
申请日：2006-09-28
申请人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/331
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

33. 发明授权

US5916733A Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5916733A
公开(公告)日：1999-06-29
申请号：US762856
申请日：1996-12-10
申请人： Haruhiko Koyama
发明人： Haruhiko Koyama
IPC分类号： G03F7/00 , H01L21/28 , H01L21/3213 , G03F7/20
CPC分类号： H01L21/32139 , G03F7/0035 , H01L21/28123 , Y10S430/143
摘要： A method of fabricating a semiconductor device includes steps of forming a first insulating film, a conductive film, a second insulating film and a selected film in sequence on a substrate. Next, a first resist pattern is formed in a first region on the selected film by means of photo-lithography. The selected film is patterned by using the first resist pattern, after which the first resist pattern is removed. Next, a second resist pattern is formed in a second region on the surface of at least the second insulating film by means of electron beam lithography. The second insulating film is patterned by using the second resist pattern, after which the second resist pattern is removed. The conductive film is then patterned by using the patterned second insulating film as a mask. The selected film is provided with an etching characteristic substantially the same as that of the conductive film so that remaining portions thereof are removed during the conductive film patterning step.
摘要翻译：制造半导体器件的方法包括在衬底上依次形成第一绝缘膜，导电膜，第二绝缘膜和选定膜的步骤。接下来，通过光刻法在所选择的膜上的第一区域中形成第一抗蚀剂图案。通过使用第一抗蚀剂图案对所选择的膜进行图案化，之后除去第一抗蚀剂图案。接下来，通过电子束光刻在至少第二绝缘膜的表面上的第二区域中形成第二抗蚀剂图案。通过使用第二抗蚀剂图案对第二绝缘膜进行图案化，之后除去第二抗蚀剂图案。然后通过使用图案化的第二绝缘膜作为掩模来将导电膜图案化。所选择的膜具有与导电膜的蚀刻特性基本相同的蚀刻特性，使得在导电膜构图步骤期间其剩余部分被去除。

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