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31. 发明申请

US20060184601A1 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US20060184601A1
公开(公告)日：2006-08-17
申请号：US11055812
申请日：2005-02-11
申请人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
发明人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准移位量计算选择信号i 指出对齐逻辑（3）输出的最高有效位是否具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6 ）。

32. 发明授权

US08566383B2 Distributed residue-checking of a floating point unit 失效
标题翻译：浮点单元的分布式残留检查
公开(公告)号：US08566383B2
公开(公告)日：2013-10-22
申请号：US12253713
申请日：2008-10-17
申请人： Son Trong Dao , Juergen Georg Haess , Michael Klaus Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Trong Dao , Juergen Georg Haess , Michael Klaus Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F11/08
CPC分类号： G06F7/483
摘要： A distributed residue checking apparatus for a floating point unit having a plurality of functional elements performing floating-point operations on a plurality of operands. The distributed residue checking apparatus includes a plurality of residue generators which generate residue values for the operands and the functional elements, and a plurality of residue checking units distributed throughout the floating point unit. Each residue checking unit receives a first residue value and a second residue value from respective residue generators and compares the first residue value to the second residue value to determine whether an error has occurred in a floating-point operation performed by a respective functional element.
摘要翻译：一种用于具有对多个操作数执行浮点运算的多个功能单元的浮点单元的分布式残留检查装置。所述分布式残差检查装置包括生成所述操作数和所述功能元件的残差值的多个残差生成器，以及分布在所述浮点单元中的多个残差检查单元。每个残差检查单元从相应的残差发生器接收第一残差值和第二残差值，并将第一残差值与第二残差值进行比较，以确定在由各个功能元件执行的浮点运算中是否发生了错误。

33. 发明申请

US20100174764A1 REUSE OF ROUNDER FOR FIXED CONVERSION OF LOG INSTRUCTIONS 有权
标题翻译：固定转换日志说明的重复使用
公开(公告)号：US20100174764A1
公开(公告)日：2010-07-08
申请号：US12350680
申请日：2009-01-08
申请人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
发明人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.
摘要翻译：一种用于将有符号固定点数转换为浮点数的方法，该浮点数包括读取与要转换的有符号固定点数相对应的输入数，确定输入数是否小于零，根据输入数量小于零或大于或等于零，通过将输入数字与符号位进行异或运算来计算第一中间结果，计算第一中间结果的前导零，基于符号位填充第一中间结果，通过将填充的第一中间结果向左移动前导零来计算第二中间结果，计算指数部分和分数部分，基于符号位有条件地增加分数部分，校正指数部分和分数部分，如果递增分数部分溢出，返回浮点数。

34. 发明授权

US07639046B2 Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit 失效
标题翻译：降低时钟门控同步电路和时钟门控同步电路的功耗的方法
公开(公告)号：US07639046B2
公开(公告)日：2009-12-29
申请号：US11850736
申请日：2007-09-06
申请人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
发明人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
IPC分类号： H03K19/00 , H03K17/16 , H03K19/003 , G06F1/00 , G05F1/10 , G05F3/02
CPC分类号： H03K19/0016
摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.
摘要翻译：一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号通过时钟门控同步电路。

35. 发明申请

US20080276140A1 SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP 有权
标题翻译：具有多重可扫描存储元件的半导体芯片和用于扫描半导体芯片上的存储元件的方法
公开(公告)号：US20080276140A1
公开(公告)日：2008-11-06
申请号：US12042944
申请日：2008-03-05
申请人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
发明人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575
摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.
摘要翻译：分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择。

36. 发明申请

US20080169842A1 DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT 失效
标题翻译：在时钟门控同步电路和时钟门控同步电路中降低功耗的设计结构
公开(公告)号：US20080169842A1
公开(公告)日：2008-07-17
申请号：US11850745
申请日：2007-09-06
申请人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
发明人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.
摘要翻译：一种用于降低时钟门控同步电路内的功耗的设计结构，所述同步电路包括至少两个连续级，其中每个级如果被激活，则逐周期地将数据信号周期传播到后级，所述两个连续级包括至少一个控制寄存器，数据寄存器和本地时钟缓冲器（LCB），其中每个级如果被激活，则将周期内存储的数据信号周期传播到后级的数据寄存器。

37. 发明申请

US20080169841A1 METHOD TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT 失效
标题翻译：降低时钟门控同步电路和时钟门控同步电路中的功耗的方法
公开(公告)号：US20080169841A1
公开(公告)日：2008-07-17
申请号：US11850736
申请日：2007-09-06
申请人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
发明人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.
摘要翻译：一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号通过时钟门控同步电路。

38. 发明申请

US20070050435A1 Leading-Zero Counter and Method to Count Leading Zeros 审中-公开
标题翻译：领先的零计数器和计算领先零的方法
公开(公告)号：US20070050435A1
公开(公告)日：2007-03-01
申请号：US11459663
申请日：2006-07-25
申请人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
发明人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
IPC分类号： G06F15/00
CPC分类号： G06F7/74
摘要： The present invention relates to a circuit comprising a Leading Zero Counter (LZC) sub-circuit driving a second sub-circuit, like a shifter or arbiter. Shifter circuits or arbiter circuits operating with fewer stages than before have a smaller delay since every stage can select between more than two inputs. This reduces the overall delay of the shifter, arbiter, etc. But for state-of-the art binary LZC circuits this requires a complex recoding between LZC and shifter circuit. In order to provide an improved leading zero circuit having an output which allows a simpler control of a post-connected sub-circuit having two or more stages and having at least one stage with three or more inputs, it is proposed to provide a LZC circuitry providing an output consisting of two or more unary encoded substrings. This removes the requirement for a recoder between LZC and shifter.
摘要翻译：本发明涉及一种包括驱动第二子电路的前导零计数器（LZC）子电路的电路，如移相器或仲裁器。移动器电路或仲裁器电路的运行次数比以前更少，延迟较小，因为每个阶段都可以在两个以上的输入之间进行选择。这减少了移位器，仲裁器等的总体延迟。但是对于最先进的二进制LZC电路，这需要LZC和移位器电路之间的复杂重新编码。为了提供具有输出的改进的前导零电路，其允许更简单地控制具有两个或更多个级的后连接子电路并且具有至少一个具有三个或更多个输入的级，所以建议提供一种LZC电路提供由两个或更多个一元编码的子串组成的输出。这消除了对LZC和移位器之间的重新编码器的要求。

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