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31. 发明申请

US20070271323A1 Compound galois field engine and galois field divider and square root engine and method 审中-公开
标题翻译：复合伽罗瓦域引擎和伽罗瓦域分配器和平方根引擎和方法
公开(公告)号：US20070271323A1
公开(公告)日：2007-11-22
申请号：US11888782
申请日：2007-08-02
申请人： Yosef Stein , Joshua Kablotsky
发明人： Yosef Stein , Joshua Kablotsky
IPC分类号： G06F15/00
CPC分类号： G06F7/726 , G06F7/552 , G06F2207/5523
摘要： A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in a Galois field reciprocal generator a first Galois field element by a first element of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m−2 times where m is the degree of the Galois field to obtain the reciprocal of the first Galois field element, and multiplying in the Galois field reciprocal engine the reciprocal of the first Galois field element by a second Galois field element for predicting the modulo remainder of the polynomial product for an irreducible polynomial to obtain the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except the first is the output of the previous Galois field linear transform; Galois field square root is achieved by inputting a Galois field element to a Galois field square root generator to obtain an output which is squared in the Galois field square root generator to predict the modulo remainder of the square of the polynomial product of an irreducible polynomial m−1 times where m is the degree of the Galois field to obtain the square root of the Galois field to obtain the square root of the Galois field element in (m−1) cycles.
摘要翻译：伽罗瓦域分频器引擎和方法将1和第一伽罗瓦域元件输入伽罗瓦域互逆发生器以获得输出，在伽罗瓦域互逆发生器中乘以伽罗瓦域互逆发生器的第一元素的第一伽罗瓦域元件，预测不可约多项式m-2倍的多项式积的平方的模余数，其中m是伽罗瓦域获得第一伽罗瓦域元的倒数的程度，并且在伽罗瓦域互逆引擎中乘以第一伽罗瓦域元素，用于预测用于不可约多项式的多项式积的模余数，以获得以m个周期的两个伽罗瓦域元素的商; 在更广泛的意义上，本发明包括用于在一系列多项式输入上执行伽罗瓦域线性变换的连续性以获得最终输出的复合Galois场引擎，其中除第一个之外的每个输入是先前伽罗瓦域线性变换的输出; 伽罗瓦域平方根通过将伽罗瓦域元素输入到伽罗瓦域平方根生成器来获得在伽罗瓦域平方根生成器中平方的输出，以预测不可约多项式m的多项式积的平方的模余数 -1次，其中m是伽罗瓦域的程度以获得伽罗瓦域的平方根，以获得（m-1）个周期中伽罗瓦域元素的平方根。

32. 发明授权

US07177891B2 Compact Galois field multiplier engine 有权
标题翻译：小型伽罗瓦域倍增引擎
公开(公告)号：US07177891B2
公开(公告)日：2007-02-13
申请号：US10395620
申请日：2003-03-24
申请人： Yosef Stein , Joshua A. Kablotsky
发明人： Yosef Stein , Joshua A. Kablotsky
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： A compact Galois field parallel multiplier engine includes a multiplier circuit for multiplying together two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit has a multiply input from the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; first and second polynomial inputs; the Galois field linear transformer circuit may include a plurality of cells configured in a matrix section and a unity matrix section wherein the unity matrix section cells represent the prediction of the remainder when the output of the multiplier circuit is a polynomial with a power less than the power of the irreducible polynomial.
摘要翻译：紧凑的伽罗瓦域并行乘法器引擎包括乘法器电路，用于将两个多项式与Galois域上的系数相乘以获得其乘积; 伽罗瓦域线性变换器电路具有来自乘法器电路的乘法输入，用于预测用于不可约多项式的多项式积的模余数; 第一和第二多项式输入; 伽罗瓦域线性变压器电路可以包括配置在矩阵部分中的多个单元和单位矩阵部分，其中当乘法器电路的输出是功率小于等于的多项式时，单位矩阵部分单元表示余数的预测不可约多项式的幂。

33. 发明授权

US06941446B2 Single instruction multiple data array cell 有权
标题翻译：单指令多数据阵列单元
公开(公告)号：US06941446B2
公开(公告)日：2005-09-06
申请号：US10090941
申请日：2002-03-05
申请人： Yosef Stein , Joshua A. Kablotsky
发明人： Yosef Stein , Joshua A. Kablotsky
IPC分类号： G06F15/00 , G06F15/80
CPC分类号： G06F15/8007
摘要： A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.
摘要翻译：用于处理数据流的单指令多数据（SIMD）阵列单元，所述阵列包括多个单元，每个单元具有用于存储所述数据流的预定区域的存储电路; 用于表示数据流的预定区域的大小和位置的位置寄存器电路; 唯一的识别号码; 以及算术逻辑单元，其响应于所述识别号码和在加载模式中对于所有小区共同的单个命令来计算用于其小区的用于接收所述直接存储器访问数据流的预定区域的唯一起始位置。在执行模式中，命令字包括可应用于所有单元的地址字段，数据字段和由算术逻辑单元执行的指令。每个单元中的算术逻辑单元使用数据字段中的数据在其存储器中的该地址处的本地值上直接执行指令。

34. 发明授权

US07912302B2 Multiprocessor decoder system and method 有权
标题翻译：多处理器解码系统及方法
公开(公告)号：US07912302B2
公开(公告)日：2011-03-22
申请号：US11725527
申请日：2007-03-19
申请人： Yosef Stein , Gordon A. Sterling
发明人： Yosef Stein , Gordon A. Sterling
IPC分类号： G06K9/36 , G06K9/46 , G06F15/16 , G06F15/80 , G06T1/20
CPC分类号： H04N19/436 , H04N19/44 , H04N19/61
摘要： Multiprocessor decoding is accomplished in a first mode by generating with a series of n processors, from a set of data macroblocks, the entropy decoding output of each data macroblock and storing the entropy decoding output of each data macroblock in n storage elements, respectively, associated with the processors and in the second mode decoding the macroblock data from its associated storage element in response to the macroblock entropy decoding output from its associated storage element stored in an nth previous period, predetermined data from one or more adjacent macroblocks, and data produced from a previous processor in the series.
摘要翻译：通过从一组数据宏块中产生一系列n个处理器，每个数据宏块的熵解码输出并分别存储在n个存储元件中的每个数据宏块的熵解码输出，分别在相关联的存储元件中存储多处理器解码处理器和第二模式响应于从其相关存储元件存储的第n个前一周期中的宏块熵解码输出，从其相关联的存储元件解码宏块数据，来自一个或多个相邻宏块的预定数据以及从系列中的以前的处理器。

35. 发明授权

US07882284B2 Compute unit with an internal bit FIFO circuit 有权
标题翻译：具有内部位FIFO电路的计算单元
公开(公告)号：US07882284B2
公开(公告)日：2011-02-01
申请号：US11728358
申请日：2007-03-26
申请人： James Wilson , Yosef Stein , Joshua A. Kablotsky
发明人： James Wilson , Yosef Stein , Joshua A. Kablotsky
IPC分类号： G06F3/00 , G06F5/00 , G11C7/10
CPC分类号： G06F5/10 , G06F5/00 , G06F5/065 , G06F5/14 , G06F9/30018 , G06F9/3824 , G06F2205/126
摘要： A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.
摘要翻译：具有内部位FIFO电路的计算单元包括至少一个数据寄存器，查找表，包括用于将查找表的一部分配置为位FIFO电路的FIFO基址，长度和读/写模式字段的配置寄存器，以及读/写指针寄存器响应于具有查找表识别字段，位字段长度和寄存器提取/存储字段的指令，用于在FIFO电路和数据寄存器之间的单个周期中选择性地传送具有指定长度的位字段。

36. 发明申请

US20090327378A1 Instruction-Based Parallel Median Filtering 有权
标题翻译：基于指令的并行中值滤波
公开(公告)号：US20090327378A1
公开(公告)日：2009-12-31
申请号：US12554500
申请日：2009-09-04
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Gregory M. Yukna
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Gregory M. Yukna
IPC分类号： G06F7/38 , G06F17/10
CPC分类号： G06F7/22 , G06F7/544 , G06F17/18 , H03H17/0263 , H03H2017/0298
摘要： An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and applies an instruction for providing one of the values to the processing step, and at least one other instruction for enabling indication of at least one of the maximum, minimum, median filter values.
摘要翻译：基于指令的并行中值滤波处理器和方法将每组输入的输入并行分成更大和更小的值; 根据输入的最小值，最大值和中值滤波器值进行排序; 处理这些值之一并将处理的值提供为输入; 并且向所述处理步骤应用用于提供所述值中的一个的指令，以及用于使得能够指示所述最大值，最小中值滤波器值中的至少一个的至少一个其他指令。

37. 发明申请

US20070226469A1 Permutable address processor and method 审中-公开
标题翻译：可置换地址处理器和方法
公开(公告)号：US20070226469A1
公开(公告)日：2007-09-27
申请号：US11368879
申请日：2006-03-06
申请人： James Wilson , Joshua Kablotsky , Yosef Stein , Colm Prendergast , Gregory Yukna , Christopher Mayer , John Hayden
发明人： James Wilson , Joshua Kablotsky , Yosef Stein , Colm Prendergast , Gregory Yukna , Christopher Mayer , John Hayden
IPC分类号： G06F9/44
CPC分类号： G06F9/30109 , G06F7/57 , G06F7/766 , G06F7/768 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3013
摘要： Accommodating a processor to process a number of different data formats includes loading a data word in a first format from a first storage device; reordering, before it reaches the arithmetic unit, the first format of the data word to a second format compatible with the native order of the arithmetic unit; and vector processing the data word in the arithmetic unit.
摘要翻译：容纳处理器以处理多个不同的数据格式包括以第一格式从第一存储设备加载数据字; 在其到达算术单元之前，将数据字的第一格式重新排序到与算术单元的本机顺序兼容的第二格式; 并向量处理算术单元中的数据字。

38. 发明授权

US08458445B2 Compute units using local luts to reduce pipeline stalls 失效
标题翻译：计算单位使用本地的油脂来减少管道摊铺
公开(公告)号：US08458445B2
公开(公告)日：2013-06-04
申请号：US13206644
申请日：2011-08-10
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
IPC分类号： G06F9/44
CPC分类号： G06F9/3001 , G06F9/345 , G06F9/3885
摘要： Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.
摘要翻译：减少处理器中的计算单元和地址单元之间的流水线停顿可以通过响应于算法的指令在计算单元中计算结果来实现; 在计算单元中存储与本算法的预定指令集合的计算结果相关的预定函数集的局部随机存取存储器阵列; 并且在计算单元内提供计算结果与相关功能的直接映射。

39. 发明授权

US08208745B2 Spatial domain video enhancement/scaling system and method 有权
标题翻译：空间域视频增强/缩放系统和方法
公开(公告)号：US08208745B2
公开(公告)日：2012-06-26
申请号：US12079547
申请日：2008-03-27
申请人： Yosef Stein , Hazarathaiah Malepati
发明人： Yosef Stein , Hazarathaiah Malepati
IPC分类号： G06K9/36 , G06K9/46 , G06K9/32 , H04N11/02
CPC分类号： H04N19/80 , H04N19/117 , H04N19/159 , H04N19/172
摘要： A method of spatial domain video enhancement/up-scaling including transforming the video input from the temporal domain to a K×K matrix of spatial domain coefficients; multiplying each spatial domain coefficient by corresponding elements of a K×K enhancement matrix to obtain enhanced spatial domain coefficients; depositing the enhanced spatial domain coefficients in the upper left K×K corner of a zero padded 2K×2K inverse transform matrix and inversely transforming them to scale the enhanced spatial domain coefficients and convert them back to video output temporal domain elements and a method of spatial domain video enhancement/down-scaling including transforming the video input from the temporal domain to a 2K×2K matrix of spatial domain coefficients; multiplying the upper left K×K corner of the 2K×2K matrix of spatial domain coefficients by the corresponding elements of a K×K enhancement matrix to obtain enhanced spatial domain coefficients; inversely transforming the K×K enhanced spatial domain coefficients to scale them and convert them back to video output temporal domain elements.
摘要翻译：一种空间域视频增强/上调的方法，包括将视频输入从时域变换为空间域系数的K×K矩阵; 将每个空间域系数乘以K×K增强矩阵的相应元素，以获得增强的空间域系数; 在零填充的2K×2K逆变换矩阵的左上角K×K角中存储增强的空间域系数，并对其进行逆变换以缩小增强的空间域系数并将其转换回视频输出时域元素和空间方法域视频增强/缩小缩放，包括将视频输入从时域变换为空间域系数的2K×2K矩阵; 将空间域系数的2K×2K矩阵的左上K×K角与K×K增强矩阵的相应元素相乘，以获得增强的空间域系数; 逆向变换K×K增强空间域系数，对其进行缩放，并将其转换回视频输出时域。

40. 发明申请

US20110296145A1 PIPELINED DIGITAL SIGNAL PROCESSOR 失效
标题翻译：管道数字信号处理器
公开(公告)号：US20110296145A1
公开(公告)日：2011-12-01
申请号：US13206644
申请日：2011-08-10
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/345 , G06F9/3885
摘要： Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.
摘要翻译：减少处理器中的计算单元和地址单元之间的流水线停顿可以通过响应于算法的指令在计算单元中计算结果来实现; 在计算单元中存储与本算法的预定指令集合的计算结果相关的预定函数集的局部随机存取存储器阵列; 并且在计算单元内提供计算结果与相关功能的直接映射。

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