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    • 37. 发明申请
    • DESIGNED-BASED YIELD MANAGEMENT SYSTEM
    • 基于设计的管理系统
    • US20120259574A1
    • 2012-10-11
    • US13080474
    • 2011-04-05
    • Chenmin HuBo SuPing ZhangYuan XuQing Zhang
    • Chenmin HuBo SuPing ZhangYuan XuQing Zhang
    • G06F19/00
    • H01L22/20H01L2924/0002H01L2924/00
    • An integrated-circuit yield improvement system includes a global signature analysis/grouping module configured to receive an integrated circuit (IC) design and identify areas in the IC design that include potential defect signatures based on the defect signatures stored in the defect signature library. The global signature analysis/grouping module can produce a global signature map indicating these areas and their associated potential defect signatures in the IC design. A local signature analysis/grouping module can identify and group local defect signatures in the IC design with the process monitoring and yield data as input, to output grouped local signatures. An intelligent learning engine can analyze the global signature map and the grouped local signatures and update some of the defect signatures in the defect signature library. A feedback loop is formed to update and renew the contents of the defect signature library for each new IC design while process and yield are improved.
    • 集成电路产量改进系统包括全局签名分析/分组模块,其被配置为接收集成电路(IC)设计,并基于存储在缺陷签名库中的缺陷签名来识别IC设计中包括潜在缺陷签名的区域。 全局签名分析/分组模块可以产生一个全局签名图,指示这些区域及其相关的潜在缺陷签名在IC设计中。 本地签名分析/分组模块可以通过流程监控和收益数据作为输入来识别和分组IC设计中的本地缺陷签名,以输出分组的本地签名。 智能学习引擎可以分析全局签名图和分组的本地签名,并更新缺陷签名库中的一些缺陷签名。 形成反馈循环,以更新和更新每个新IC设计的缺陷签名库的内容,同时改进处理和产量。