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31. 发明授权

US07728563B2 Fast voltage regulators for charge pumps 有权
标题翻译：快速电压调节器
公开(公告)号：US07728563B2
公开(公告)日：2010-06-01
申请号：US12340571
申请日：2008-12-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/613
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

32. 发明申请

US20090323415A1 FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL 有权
标题翻译：闪存存储器阵列系统，包括顶盖存储器单元
公开(公告)号：US20090323415A1
公开(公告)日：2009-12-31
申请号：US12507783
申请日：2009-07-22
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

33. 发明授权

US07616028B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US07616028B2
公开(公告)日：2009-11-10
申请号：US11942665
申请日：2007-11-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

34. 发明授权

US07436258B2 Multi-operational amplifier system 有权
标题翻译：多运算放大器系统
公开(公告)号：US07436258B2
公开(公告)日：2008-10-14
申请号：US11830720
申请日：2007-07-30
申请人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin
发明人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin
IPC分类号： H03F1/14
CPC分类号： H03F3/45192 , H03F3/211 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2203/21109 , H03F2203/21145 , H03F2203/45138 , H03F2203/45288 , H03F2203/45541 , H03F2203/45618 , H03F2203/45626 , H03F2203/45722 , H03F2203/45728 , H03F2203/7206 , H03F2203/7215
摘要： A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.
摘要翻译：多运算放大器系统包括多个运算放大器和用于配置多个运算放大器的控制器。运算放大器可以被选择性地配置成单独操作或与其他运算放大器组合运行。运算放大器可能具有不同的公共节点输入。在一个方面，可以从PMOS，N型NMOS和NZ NMOS输入的组中选择不同的输入。运算放大器可以包括被布置为差分对的不同输入。

35. 发明授权

US06490212B1 Bitline precharge matching 有权
标题翻译：位线预充电匹配
公开(公告)号：US06490212B1
公开(公告)日：2002-12-03
申请号：US09904160
申请日：2001-07-11
申请人： Hung Q. Nguyen , Nianglamching Hangzo , Sang Thanh Nguyen
发明人： Hung Q. Nguyen , Nianglamching Hangzo , Sang Thanh Nguyen
IPC分类号： G11C700
CPC分类号： G11C16/28 , G11C7/062 , G11C7/12 , G11C7/14
摘要： A memory device includes a sense circuit comprising a sense amplifier, a reference sense circuit and a comparator. The sense amplifier detects a signal on a bit line associated with a column of memory cells in a memory array. The reference sense circuit detects a signal on a reference bit line associated with a column of reference cells in the memory array. The comparator compares the outputs of the sense amplifier and the reference sense circuit and provides a signal indicative of the contents of the read memory cell. In response to a transition of an address, the bit line and the reference bit line are precharged prior to reading of the memory cell. The reference sense circuit includes a selectable load that is disabled during the initial time after the address transition so that the bit line and the reference bit line rises substantially identically and then enabled to allow the reference bit line to settle to a steady state.
摘要翻译：存储器件包括读出电路，其包括读出放大器，参考检测电路和比较器。读出放大器检测与存储器阵列中的一列存储器单元相关联的位线上的信号。参考检测电路检测与存储器阵列中的参考单元列相关联的参考位线上的信号。比较器比较读出放大器和参考检测电路的输出，并提供指示读取存储单元的内容的信号。响应于地址的转换，位线和参考位线在读取存储器单元之前被预充电。参考检测电路包括在地址转换之后的初始时间期间禁用的可选负载，使得位线和参考位线基本上相同地上升，然后使能使得参考位线稳定到稳定状态。

36. 发明授权

US08232833B2 Charge pump systems and methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US08232833B2
公开(公告)日：2012-07-31
申请号：US11805765
申请日：2007-05-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F3/24 , H02M3/18
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

37. 发明授权

US08049535B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US08049535B2
公开(公告)日：2011-11-01
申请号：US12972974
申请日：2010-12-20
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

38. 发明申请

US20110122693A1 FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL 有权
标题翻译：闪存存储器阵列系统，包括顶盖存储器单元
公开(公告)号：US20110122693A1
公开(公告)日：2011-05-26
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/10 , G11C16/08
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

39. 发明申请

US20100188138A1 Fast Start Charge Pump for Voltage Regulators 有权
标题翻译：用于稳压器的快速启动电荷泵
公开(公告)号：US20100188138A1
公开(公告)日：2010-07-29
申请号：US12726249
申请日：2010-03-17
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M1/36 , H02M1/44
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

40. 发明授权

US07663921B2 Flash memory array with a top gate line dynamically coupled to a word line 有权
标题翻译：具有动态耦合到字线的顶栅线的闪存阵列
公开(公告)号：US07663921B2
公开(公告)日：2010-02-16
申请号：US12267519
申请日：2008-11-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.
摘要翻译：公开了包括排列在扇区中的存储单元的系统和方法。在一个示例性实施方案中，每个存储单元可以包括顶部栅极，源极，耦合扇区中的存储器单元的顶栅极线和将存储器单元耦合在一起的字线。此外，顶栅线可以动态耦合到字线。其它示例性实现可涉及用于驱动字线和/或顶栅线，多电平存储器单元和/或浮栅线特征的驱动器。

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