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31. 发明申请

US20140001520A1 CONTACT RESISTANCE REDUCED P-MOS TRANSISTORS EMPLOYING GE-RICH CONTACT LAYER 审中-公开
标题翻译：接触电阻减少的P-MOS晶体管采用GE-RICH接触层
公开(公告)号：US20140001520A1
公开(公告)日：2014-01-02
申请号：US13539200
申请日：2012-06-29
申请人： Glenn A. Glass , Anand S. Murthy
发明人： Glenn A. Glass , Anand S. Murthy
IPC分类号： H01L29/78 , H01L21/336
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
摘要翻译：公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。这些技术可以例如使用例如硅或硅锗（SiGe）源极/漏极区域上的一系列金属的标准接触堆叠来实现。根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂的锗 - 锡合金层，以显着降低接触电阻。根据本公开，包括平面和非平面晶体管结构（例如，FinFET和纳米线晶体管）都可以显示许多晶体管配置和合适的制造工艺。这些技术特别适用于实现p型器件，但如果需要，可以用于n型器件。

32. 发明申请

US20140285980A1 CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR 有权
标题翻译：应变诱导缓冲器对电绝缘子的转换
公开(公告)号：US20140285980A1
公开(公告)日：2014-09-25
申请号：US13976068
申请日：2012-04-13
申请人： Annalisa Cappellani , Van H. Le , Glenn A. Glass , Kelin J. Kuhn , Stephen M. Cea
发明人： Annalisa Cappellani , Van H. Le , Glenn A. Glass , Kelin J. Kuhn , Stephen M. Cea
IPC分类号： H01L29/06 , H01L21/02 , H05K1/18
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02236 , H01L21/02238 , H01L21/02241 , H01L21/02255 , H01L21/02304 , H01L21/02439 , H01L21/0245 , H01L21/02455 , H01L21/02488 , H01L21/02532 , H01L21/306 , H01L21/76 , H01L21/7624 , H01L21/76283 , H01L29/0603 , H01L29/0642 , H01L29/0653 , H01L29/0657 , H01L29/1054 , H01L29/7378 , H01L29/785 , H01L33/12 , H05K1/18
摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
摘要翻译：公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些在应变诱导缓冲器上并具有埋入的电绝缘体层。例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

33. 发明授权

US07812394B2 CMOS transistor junction regions formed by a CVD etching and deposition sequence 有权
标题翻译：通过CVD蚀刻和沉积顺序形成CMOS晶体管结区域
公开(公告)号：US07812394B2
公开(公告)日：2010-10-12
申请号：US12250191
申请日：2008-10-13
申请人： Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
发明人： Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
IPC分类号： H01L31/119
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/517 , H01L29/66628 , H01L29/7834
摘要： This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
摘要翻译：本发明增加了替代源极 - 漏极cMOS晶体管的技术。方法可以包括使用一个设备组来蚀刻衬底材料中的凹部，然后在另一个设备组中进行沉积。公开了一种在没有大气暴露的情况下在相同的反应器中进行蚀刻和随后的沉积的方法。用于替代源极 - 漏极应用的源极 - 漏极凹槽的原位蚀刻提供了优于现有技术的非原位蚀刻的几个优点。晶体管驱动电流通过以下因素得到改善：（1）当被蚀刻的表面暴露于大气中时，消除硅 - 外延层界面的污染，（2）精确控制蚀刻凹槽的形状。沉积可以通过各种技术进行，包括选择性和非选择性方法。在覆盖层沉积的情况下，还提出了避免在性能关键区域中无定形沉积的措施。

34. 发明申请

US20110006344A1 Method for improving transistor performance through reducing the salicide interface resistance 审中-公开
公开(公告)号：US20110006344A1
公开(公告)日：2011-01-13
申请号：US12655323
申请日：2009-12-29
申请人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
发明人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41725 , H01L29/6628 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , H01L29/7842 , Y10S438/933
摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

35. 发明授权

US07274055B2 Method for improving transistor performance through reducing the salicide interface resistance 有权
标题翻译：通过降低硅化物界面电阻来提高晶体管性能的方法
公开(公告)号：US07274055B2
公开(公告)日：2007-09-25
申请号：US11171097
申请日：2005-06-29
申请人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
发明人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41725 , H01L29/6628 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , H01L29/7842 , Y10S438/933
摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
摘要翻译：本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻。基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。可以掺杂硅锗以进一步调整其电性能。降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

36. 发明授权

US06949482B2 Method for improving transistor performance through reducing the salicide interface resistance 有权
标题翻译：通过降低硅化物界面电阻来提高晶体管性能的方法
公开(公告)号：US06949482B2
公开(公告)日：2005-09-27
申请号：US10731269
申请日：2003-12-08
申请人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
发明人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
IPC分类号： H01L21/285 , H01L21/336 , H01L29/78 , H01L21/00
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41725 , H01L29/6628 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , H01L29/7842 , Y10S438/933
摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
摘要翻译：本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻。基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。可以掺杂硅锗以进一步调整其电性能。降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

37. 发明申请

US20110101418A1 Method for improving transistor performance through reducing the salicide interface resistance 有权
标题翻译：通过降低硅化物界面电阻来提高晶体管性能的方法
公开(公告)号：US20110101418A1
公开(公告)日：2011-05-05
申请号：US12655341
申请日：2009-12-29
申请人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
发明人： Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
IPC分类号： H01L29/161 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41725 , H01L29/6628 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , H01L29/7842 , Y10S438/933
摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
摘要翻译：本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻。基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。可以掺杂硅锗以进一步调整其电性能。降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

38. 发明授权

US09559160B2 Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition 有权
标题翻译：具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件
公开(公告)号：US09559160B2
公开(公告)日：2017-01-31
申请号：US13996506
申请日：2011-12-23
申请人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
发明人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
IPC分类号： H01L29/04 , H01L29/66 , H01L29/775 , H01L27/12 , B82Y10/00 , B82Y40/00 , H01L29/06 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/045 , B82Y10/00 , B82Y40/00 , H01L21/823821 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78687 , H01L29/78696
摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
摘要翻译：描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座，将第二纳米线或半导体本体与晶体衬底隔离。

39. 发明授权

US09129827B2 Conversion of strain-inducing buffer to electrical insulator 有权
标题翻译：应变诱导缓冲液转化为电绝缘体
公开(公告)号：US09129827B2
公开(公告)日：2015-09-08
申请号：US13976068
申请日：2012-04-13
申请人： Annalisa Cappellani , Van H. Le , Glenn A. Glass , Kelin J. Kuhn , Stephen M. Cea
发明人： Annalisa Cappellani , Van H. Le , Glenn A. Glass , Kelin J. Kuhn , Stephen M. Cea
IPC分类号： H01L33/12 , H01L29/06 , H01L21/76 , H01L21/02 , H05K1/18 , H01L29/66 , H01L29/78 , H01L29/10
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02236 , H01L21/02238 , H01L21/02241 , H01L21/02255 , H01L21/02304 , H01L21/02439 , H01L21/0245 , H01L21/02455 , H01L21/02488 , H01L21/02532 , H01L21/306 , H01L21/76 , H01L21/7624 , H01L21/76283 , H01L29/0603 , H01L29/0642 , H01L29/0653 , H01L29/0657 , H01L29/1054 , H01L29/7378 , H01L29/785 , H01L33/12 , H05K1/18
摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
摘要翻译：公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些在应变诱导缓冲器上并具有埋入的电绝缘体层。例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fe 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

40. 发明申请

US20130320294A1 COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICONDUCTOR BODIES WITH DIFFERING MATERIAL ORIENTATION OR COMPOSITION 有权
标题翻译：具有不同材料取向或组成的纳米线或半导体器件的共面衬底半导体器件
公开(公告)号：US20130320294A1
公开(公告)日：2013-12-05
申请号：US13996506
申请日：2011-12-23
申请人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
发明人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , B82Y10/00 , B82Y40/00 , H01L21/823821 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78687 , H01L29/78696
摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
摘要翻译：描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座将第二纳米线或半导体本体与晶体衬底隔离。

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