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31. 发明申请

US20130283064A1 METHOD AND APPARATUS TO PROCESS SHA-1 SECURE HASHING ALGORITHM 有权
标题翻译：用于处理SHA-1安全冲洗算法的方法和装置
公开(公告)号：US20130283064A1
公开(公告)日：2013-10-24
申请号：US13976293
申请日：2011-12-22
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F21/60
CPC分类号： G06F21/602 , G06F9/30007 , H04L9/0643 , H04L9/3239 , H04L2209/122
摘要： A processor includes an instruction decoder to receive a first instruction to process a SHA-1 hash algorithm, the first instruction having a first operand to store a SHA-1 state, a second operand to store a plurality of messages, and a third operand to specify a hash function, and an execution unit coupled to the instruction decoder to perform a plurality of rounds of the SHA-1 hash algorithm on the SHA-1 state specified in the first operand and the plurality of messages specified in the second operand, using the hash function specified in the third operand.
摘要翻译：处理器包括指令解码器，用于接收处理SHA-1散列算法的第一指令，所述第一指令具有用于存储SHA-1状态的第一操作数，存储多个消息的第二操作数和第三操作数，指定散列函数，以及执行单元，其耦合到指令解码器，以在第一操作数中指定的SHA-1状态和第二操作数中指定的多个消息中执行多轮SHA-1散列算法，使用第三个操作数中指定的散列函数。

32. 发明授权

US09740484B2 Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage 有权
公开(公告)号：US09740484B2
公开(公告)日：2017-08-22
申请号：US13995494
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon , Robert S. Chappell
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon , Robert S. Chappell
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/34
摘要： An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.

33. 发明授权

US09436435B2 Apparatus and method for vector instructions for large integer arithmetic 有权
标题翻译：用于大整数运算的向量指令的装置和方法
公开(公告)号：US09436435B2
公开(公告)日：2016-09-06
申请号：US13996529
申请日：2011-12-23
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Vinodh Gopal , Wajdi K. Feghali , Sean M. Gulley , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Vinodh Gopal , Wajdi K. Feghali , Sean M. Gulley , Martin G. Dixon
IPC分类号： G06F7/525 , G06F7/57 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3016 , G06F7/525 , G06F7/57 , G06F9/3001 , G06F9/30036 , G06F9/3893
摘要： An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.
摘要翻译：描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

34. 发明申请

US20160092688A1 INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM3 CRYPTOGRAPHIC HASHING FUNCTIONALITY 有权
标题翻译：说明和逻辑提供SIMD SM3 CRYPTOGRAPHIC HASHING功能
公开(公告)号：US20160092688A1
公开(公告)日：2016-03-31
申请号：US14498931
申请日：2014-09-26
申请人： Gilbert M. Wolrich , Vinodh Gopal , Sean M. Gulley , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Sean M. Gulley , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F21/60 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30007 , G06F9/30036 , G06F21/72
摘要： Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.
摘要翻译：说明和逻辑提供SIMD SM3加密散列功能。一些实施例包括处理器，包括：解码器，用于解码SIMD SM3消息扩展的指令，指定第一和第二源数据操作数集合以及扩展范围。响应于指令的处理器执行单元从由指定扩展范围确定的第一和第二源数据操作数集执行多个SM3消息扩展，并将结果存储到SIMD目的地寄存器中。一些实施例还从中间散列值输入，源数据集和圆常数集合执行散列算法的SIMD SM3散列圆切片部分的指令。处理器执行单元在源数据集上执行一组SM3散列循环迭代，应用中间散列值输入和循环常数集合，并将新的散列值结果存储在SIMD目的寄存器中。

35. 发明授权

US09251374B2 Instructions to perform JH cryptographic hashing 有权
标题翻译：执行JH密码散列的说明
公开(公告)号：US09251374B2
公开(公告)日：2016-02-02
申请号：US13992225
申请日：2011-12-22
申请人： Kirk S. Yap , Gilbert M. Wolrich , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F21/00 , G06F21/64 , H04L9/06
CPC分类号： G06F21/64 , H04L9/0643 , H04L2209/12
摘要： A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
摘要翻译：描述了一种方法。该方法包括在JH状态下执行一个或多个JH_SBOX_L指令来执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换。

36. 发明授权

US09128698B2 Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction 有权
标题翻译：响应于单个指令执行旋转和异或的系统，设备和方法
公开(公告)号：US09128698B2
公开(公告)日：2015-09-08
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的地操作数和即时价值。

37. 发明申请

US20150098563A1 Generating Multiple Secure Hashes from a Single Data Buffer 有权
标题翻译：从单个数据缓冲区生成多个安全哈希
公开(公告)号：US20150098563A1
公开(公告)日：2015-04-09
申请号：US14050326
申请日：2013-10-09
申请人： Sean M. Gulley , Vinodh Gopal , Wajdi K. Feghali , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Vinodh Gopal , Wajdi K. Feghali , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , G06F9/30007 , G06F21/72 , H04L9/3242 , H04L2209/12 , H04L2209/125 , H04L2209/20
摘要： One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.
摘要翻译：一个实施例提供了一种装置。该装置包括单个指令多数据（SIMD）散列模块，其被配置为将长度为L的消息的至少第一部分分配给数量（S）个段，该消息包括多个数据元素序列，每个序列包括 S个数据元素，分配给相应段的每个序列中的相应数据元素，每个段包括N个数据元素块，并且并行地对S个段进行散列，导致S段摘要，基于S个散列摘要至少部分地在初始值上存储S哈希摘要; 填充模块，被配置为填补余数，剩余部分对应于消息的第二部分，与消息的长度L相关的第二部分，段的数量和块大小; 以及非SIMD散列模块，被配置为对填充的余数进行散列，产生附加的散列摘要并存储附加散列摘要。

38. 发明申请

US20140195817A1 THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS 审中-公开
标题翻译：三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
公开(公告)号：US20140195817A1
公开(公告)日：2014-07-10
申请号：US13996527
申请日：2011-12-23
申请人： Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
发明人： Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
IPC分类号： G06F21/60 , G06F9/30
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30181
摘要： A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.
摘要翻译：描述了一种方法，其包括在半导体芯片上实现的指令执行流水线内执行以下操作：通过执行单个指令对三个输入向量操作数相加; 并且，即使求和的结果产生比设计用于传送求和的电路更多的位能够传输，也不会提高任何算术标记。

39. 发明申请

US20140189369A1 Instructions Processors, Methods, and Systems to Process Secure Hash Algorithms 有权
标题翻译：指令处理器，方法和系统来处理安全散列算法
公开(公告)号：US20140189369A1
公开(公告)日：2014-07-03
申请号：US13843141
申请日：2013-03-15
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： G06F21/72
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译：方面的方法包括接收指令。该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。该指令指示第二打包数据的第二来源。第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。该方法还包括响应于指令将结果存储在由指令指示的目的地中。结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

40. 发明申请

US20140095844A1 Systems, Apparatuses, and Methods for Performing Rotate and XOR in Response to a Single Instruction 有权
标题翻译：用于对单个指令进行旋转和异或运算的系统，设备和方法
公开(公告)号：US20140095844A1
公开(公告)日：2014-04-03
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的操作数和即时价值。

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