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31. 发明授权

US07697338B2 Systems for controlled boosting in non-volatile memory soft programming 有权
标题翻译：用于非易失性存储器软编程中受控升压的系统
公开(公告)号：US07697338B2
公开(公告)日：2010-04-13
申请号：US11560751
申请日：2006-11-16
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3404
摘要： A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The level of boosting in the channel region of the inhibited NAND string is governed by the pre-charge voltage and the soft programming voltage. By controlling the pre-charge voltage, more reliable and consistent channel boosting can be achieved. In one embodiment, the pre-charge voltage is increased between applications of the soft programming voltage to reduce or eliminate a rise in the channel's boosted potential. In one embodiment, the soft programming pre-charge voltage level(s) is determined during testing that is performed as part of a manufacturing process.
摘要翻译：软编程预充电电压在非易失性存储器件的软编程操作期间提供升压控制。可以将预充电电压施加到一块存储器单元的字线，以使得能够预先对NAND串的通道区进行预编程以禁止软编程。被禁止的NAND串的通道区域中的升压电平由预充电电压和软编程电压控制。通过控制预充电电压，可以实现更可靠和一致的通道增压。在一个实施例中，在应用软编程电压之间增加预充电电压以减少或消除通道的升压电位的上升。在一个实施例中，软编程预充电电压电平在作为制造过程的一部分执行的测试期间被确定。

32. 发明授权

US07672165B2 Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices 有权
标题翻译：用于主动升压以最小化闪存器件的相邻栅极之间的电容耦合效应的方法
公开(公告)号：US07672165B2
公开(公告)日：2010-03-02
申请号：US12031640
申请日：2008-02-14
申请人： Tuan D Pham , Masaaki Higashitani , Hao Fang Fang , Gerrit Jan Hemink
发明人： Tuan D Pham , Masaaki Higashitani , Hao Fang Fang , Gerrit Jan Hemink
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , H01L23/5222 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在门中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

33. 发明授权

US07408804B2 Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells 有权
标题翻译：用于软编程非易失性存储器的系统，其利用存储器单元的子集的单独验证和附加的软编程
公开(公告)号：US07408804B2
公开(公告)日：2008-08-05
申请号：US11296071
申请日：2005-12-06
申请人： Gerrit Jan Hemink , Teruhiko Kamei
发明人： Gerrit Jan Hemink , Teruhiko Kamei
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.
摘要翻译：一组非易失性存储元件被划分为用于软编程的子集，以便更软地编程较慢的软编程元件。整个元素组被软编程，直到被验证为软编程（或直到第一个元素子集被验证为软编程，而不是第二个子集验证）。在集合被验证为软编程之后，元素的第一子集被禁止进一步的软编程，而在第二子元素上执行附加的软编程。第二子集可以包括较慢的软编程元素。然后可以将第二个子集进行软编程验证，同时将第一个子集排除在验证之外。软编程和验证第二个子集可以继续，直到它被验证为软编程。可以使用不同的步长来增加软编程信号的大小，具体取决于软编程和验证哪个子集。

34. 发明申请

US20080084747A1 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE 有权
标题翻译：减少非挥发性储存中的程序干扰
公开(公告)号：US20080084747A1
公开(公告)日：2008-04-10
申请号：US11535628
申请日：2006-09-27
申请人： Gerrit Jan Hemink , Shih-Chung Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee
IPC分类号： G11C16/04 , G11C7/00 , G11C11/34
CPC分类号： G11C16/0483 , G11C7/1006 , G11C11/5628 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.
摘要翻译：非易失性半导体存储系统以通过在可以被部分编程的连接的非易失性存储元件的一个或多个字线上施加更高的升压电压来减少编程干扰的方式进行编程。

35. 发明授权

US07355889B2 Method for programming non-volatile memory with reduced program disturb using modified pass voltages 有权
标题翻译：使用修改的通过电压对具有减少的编程干扰的非易失性存储器进行编程的方法
公开(公告)号：US07355889B2
公开(公告)日：2008-04-08
申请号：US11313023
申请日：2005-12-19
申请人： Gerrit Jan Hemink , Ken Oowada
发明人： Gerrit Jan Hemink , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C2211/5621
摘要： Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.
摘要翻译：非易失性存储元件以通过使用修改的通过电压来减少编程干扰的方式被编程。特别地，在与所选择的字线相关联的所选择的存储元件的编程期间，将较高的通过电压施加到与组中的先前编程的非易失性存储元件相关联的字线，而不是与未编程和/或部分相关联的字线在集合中编程的非易失性存储元件。通过电压足够高以平衡所选字线的源极和漏极侧上的沟道电位和/或减小在升压的沟道区之间的电荷泄漏。可选地，通过在所选择的字线和接收较高通过电压的字线之间的一个或多个字线上施加降低的电压，在升压的沟道区之间形成隔离区。

36. 发明申请

US20070279993A1 VERIFY OPERATION FOR NON-VOLATILE STORAGE USING DIFFERENT VOLTAGES 有权
标题翻译：使用不同电压进行非易失存储的验证操作
公开(公告)号：US20070279993A1
公开(公告)日：2007-12-06
申请号：US11421667
申请日：2006-06-01
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/10 , G11C16/3418
摘要： When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage.
摘要翻译：当执行数据检测操作时，包括在编程非易失性存储元件期间（或在某些情况下，在编程之后的读取操作期间）中的验证操作，第一电压被用于已经经过编程的未被选择的字线对未经过编程操作的未选字线使用第二电压。在一些实施例中，第二电压低于第一电压。

37. 发明申请

US20070279985A1 SYSTEM FOR VERIFYING NON-VOLATILE STORAGE USING DIFFERENT VOLTAGES 有权
标题翻译：使用不同电压验证非易失性存储的系统
公开(公告)号：US20070279985A1
公开(公告)日：2007-12-06
申请号：US11421682
申请日：2006-06-01
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/06 , G11C16/04 , G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage.
摘要翻译：当执行数据检测操作时，包括在编程非易失性存储元件期间（或在某些情况下，在编程之后的读取操作期间）中的验证操作，第一电压被用于已经经过编程的未被选择的字线对未经过编程操作的未选字线使用第二电压。在一些实施例中，第二电压低于第一电压。

38. 发明授权

US07092290B2 High speed programming system with reduced over programming 有权
标题翻译：具有减少编程的高速编程系统
公开(公告)号：US07092290B2
公开(公告)日：2006-08-15
申请号：US10990702
申请日：2004-11-16
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3468 , G11C16/3486 , G11C2216/14
摘要： A program pulse is applied to a set of non-volatile storage elements. The magnitude of the program pulse is chosen to be low enough such that no non-volatile storage elements will be over programmed. The non-volatile storage elements are tested to determine whether at least one non-volatile storage element (or some other minimum number) has been programmed past a test threshold. If so, the set of non-volatile memory elements is considered to have one or more fast programming non-volatile storage elements and future programming is performed using a smaller increment value for subsequent program pulses. If the set of non-volatile memory elements is not determined to have one or more fast programming non-volatile storage elements, then a larger increment value is used for subsequent program pulses until one non-volatile storage element (or some other minimum number) has been programmed past the test threshold, at which point the smaller increment value is used for subsequent program pulses.
摘要翻译：将编程脉冲施加到一组非易失性存储元件。选择程序脉冲的幅度足够低，使得不会对非易失性存储元件进行过度编程。测试非易失性存储元件以确定至少一个非易失性存储元件（或一些其他最小数量）是否被编程超过测试阈值。如果是这样，则该组非易失性存储器元件被认为具有一个或多个快速编程非易失性存储元件，并且对于随后的编程脉冲使用较小的增量值来执行将来的编程。如果该组非易失性存储器元件未被确定为具有一个或多个快速编程非易失性存储元件，则对于后续的编程脉冲使用较大的增量值，直到一个非易失性存储元件（或一些其它最小数量）已被编程超过测试阈值，此时较小的增量值用于后续编程脉冲。

39. 发明申请

US20120307558A1 APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB 有权
公开(公告)号：US20120307558A1
公开(公告)日：2012-12-06
申请号：US13588202
申请日：2012-08-17
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

40. 发明申请

US20120236654A1 PROGRAMMING NON-VOLATILE MEMORY WITH VARIABLE INITIAL PROGRAMMING PULSE 有权
标题翻译：编程具有可变初始编程脉冲的非易失性存储器
公开(公告)号：US20120236654A1
公开(公告)日：2012-09-20
申请号：US13488625
申请日：2012-06-05
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3468 , G11C16/3486 , G11C2211/5621 , G11C2211/5648
摘要： Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse associated with achieving an intermediate result for a respective programming process is identified, a pulse increment between programming pulses is decreased for the respective programming process while continuing the respective programming process to program non-volatile storage elements to the respective one or more targets and the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process.
摘要翻译：对多个非易失性存储元件执行多个编程处理。编程过程中的每一个操作以使用编程脉冲将至少一个非易失性存储元件的子集编程到一组目标条件。对于编程过程的至少一个子集，识别与实现相应编程处理的中间结果相关联的编程脉冲，针对相应的编程过程减少编程脉冲之间的脉冲增量，同时继续相应的编程处理，易失性存储元件到相应的一个或多个目标，并且所识别的编程脉冲用于调整用于后续编程处理的起始编程电压。

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