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31. 发明申请

US20090162977A1 Non-Volatile Memory Fabrication And Isolation For Composite Charge Storage Structures 有权
标题翻译：用于复合电荷存储结构的非易失性存储器制造和隔离
公开(公告)号：US20090162977A1
公开(公告)日：2009-06-25
申请号：US11960518
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译：制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。

32. 发明申请

US20090155967A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权
标题翻译：使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
公开(公告)号：US20090155967A1
公开(公告)日：2009-06-18
申请号：US11958941
申请日：2007-12-18
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

33. 发明申请

US20080242006A1 METHODS OF FORMING NAND FLASH MEMORY WITH FIXED CHARGE 有权
标题翻译：形成具有固定电荷的NAND闪存存储器的方法
公开(公告)号：US20080242006A1
公开(公告)日：2008-10-02
申请号：US11692961
申请日：2007-03-29
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： H01L21/77
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

34. 发明申请

US20080239819A1 NAND FLASH MEMORY WITH FIXED CHARGE 有权
标题翻译：具有固定充电的NAND闪存
公开(公告)号：US20080239819A1
公开(公告)日：2008-10-02
申请号：US11692958
申请日：2007-03-29
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324 , H01L29/7881
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

35. 发明申请

US20080171415A1 Methods of Forming NAND Memory with Virtual Channel 有权
标题翻译：用虚拟通道形成NAND存储器的方法
公开(公告)号：US20080171415A1
公开(公告)日：2008-07-17
申请号：US11626784
申请日：2007-01-24
申请人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
发明人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

36. 发明授权

US08193055B1 Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution 有权
标题翻译：使用聚合物溶液形成包括自对准金属纳米点的浮栅的存储器的方法
公开(公告)号：US08193055B1
公开(公告)日：2012-06-05
申请号：US11958875
申请日：2007-12-18
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , B82Y40/00 , H01L27/11521 , H01L29/42332 , Y10S977/72 , Y10S977/81
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在一个示例性方法中，将金属盐离子加入到共聚物溶液的芯中。金属盐还原导致金属原子在芯中聚集，形成金属纳米点。使用旋涂或浸涂将共聚物溶液施加到基板上的栅极氧化物上。由于共聚物构型，纳米点被保持在栅极氧化物上的均匀的2D栅格中。选择聚合物以在纳米点之间提供期望的纳米尺寸和间隔。聚合物固化和去除过程使栅极氧化物上的纳米点离开。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

37. 发明申请

US20100240182A1 Spacer Patterns Using Assist Layer For High Density Semiconductor Devices 有权
标题翻译：使用高密度半导体器件辅助层的间隔图
公开(公告)号：US20100240182A1
公开(公告)日：2010-09-23
申请号：US12791103
申请日：2010-06-01
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小光刻可分辨元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

38. 发明授权

US07795080B2 Methods of forming integrated circuit devices using composite spacer structures 有权
标题翻译：使用复合间隔结构形成集成电路器件的方法
公开(公告)号：US07795080B2
公开(公告)日：2010-09-14
申请号：US12014689
申请日：2008-01-15
申请人： Takashi Orimoto , George Matamis , James Kai , Tuan Pham , Masaaki Higashitani , Henry Chien
发明人： Takashi Orimoto , George Matamis , James Kai , Tuan Pham , Masaaki Higashitani , Henry Chien
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521
摘要： Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.
摘要翻译：使用复合间隔物形成工艺提供制造集成电路器件的方法。当形成设备的选择特征时，使用复合间隔物结构来图案化和蚀刻层堆叠。复合存储结构包括由第一隔离物材料层形成的第一间隔物和由第二隔离物材料层形成的第二和第三间隔物。该方法适用于制造具有小于所使用的光刻工艺的最小可分辨特征尺寸的线和空间尺寸的装置。此外，等于线和空间尺寸小于最小特征尺寸是可能的。在一个实施例中，使用复合间隔结构形成双控制非易失性闪存存储元件阵列。当形成衬底的活性区域时，具有叠层的叠层和隔离区之间的复合间隔结构有利于条之间的等长长度和隔离区。

39. 发明授权

US07773403B2 Spacer patterns using assist layer for high density semiconductor devices 有权
标题翻译：使用辅助层的高密度半导体器件的间隔图案
公开(公告)号：US07773403B2
公开(公告)日：2010-08-10
申请号：US11623315
申请日：2007-01-15
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： G11C5/06
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻解析的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

40. 发明申请

US20100190319A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权
标题翻译：使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
公开(公告)号：US20100190319A1
公开(公告)日：2010-07-29
申请号：US12754408
申请日：2010-04-05
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

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