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31. 发明授权

US06370073B2 Single-port multi-bank memory system having read and write buffers and method of operating same 有权
标题翻译：具有读写缓冲器的单端口多行存储器系统及其操作方法
公开(公告)号：US06370073B2
公开(公告)日：2002-04-09
申请号：US09768908
申请日：2001-01-23
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C700
CPC分类号： G11C11/005 , G06F12/0893 , G06F2212/3042 , G11C11/406 , G11C11/40618
摘要： A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A single-port multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing memory refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. Both the read buffer and the write buffer can be constructed of DRAM cells.
摘要翻译：一种用于处理需要周期性刷新操作的DRAM阵列或其他存储器阵列的刷新的方法和装置，使得刷新不需要显式控制信号，也不需要在存储器阵列和外部存取客户端之间握手通信。该方法和装置处理外部访问和刷新操作，使得刷新操作在任何情况下不干扰外部访问。因此，可以从DRAM或1晶体管单元构建SRAM兼容器件。单端口多行刷新方案用于减少内存刷新操作和内存数据访问操作之间的冲突次数。读取缓冲器用于缓冲读取数据，从而允许当连续的读取访问长时间到达特定存储体的地址范围时执行存储器刷新操作。写入缓冲器用于缓冲写入数据，从而允许在连续的写入访问长时间到达特定存储体的地址范围时执行存储器刷新操作。读缓冲器和写缓冲器都可以由DRAM单元构成。

32. 发明授权

US06222785B1 Method and apparatus for refreshing a semiconductor memory using idle memory cycles 有权
标题翻译：使用空闲存储器周期刷新半导体存储器的方法和装置
公开(公告)号：US06222785B1
公开(公告)日：2001-04-24
申请号：US09234778
申请日：1999-01-20
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C700
CPC分类号： G11C11/40618 , G06F13/1636 , G11C11/406 , G11C11/4076
摘要： A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does not require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controller ensures that there will always be enough idle cycles in which the memory array can be refreshed.
摘要翻译：提供了以不需要大量外部控制的方式控制必须刷新的存储器（例如DRAM）的存储器系统。在一个实施例中，存储器系统包括存储器控制器和通过系统总线耦合的存储器块。存储器块包括必须定期刷新以保持有效数据的存储器单元阵列。存储器块还包括刷新控制电路，其在存储器阵列的空闲周期期间刷新存储器单元。存储器控制器在预定的刷新周期期间监视系统总线上的空闲周期数。如果所监视的空闲周期的数量小于预定的空闲周期数，则存储器控制器在系统总线上强制所需的空闲周期数。因此，存储器控制器确保总是存在可以刷新存储器阵列的足够的空闲周期。

33. 发明授权

US06215497B1 Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system 失效
标题翻译：用于使计算机图形系统中的多存储体DRAM的随机存取带宽最大化的方法和装置
公开(公告)号：US06215497B1
公开(公告)日：2001-04-10
申请号：US09133475
申请日：1998-08-12
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G06T1700
CPC分类号： G06T1/60
摘要： A graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator or an external central processing unit (CPU). The embedded DRAM memory is logically divided into a plurality of independent banks, thereby resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The memory access time for any transaction (e.g., a bank-conflict access) is no greater than the memory cycle time plus the memory access time minus 1 clock cycle.
摘要翻译：具有2-D图形加速器，3-D图形加速器和嵌入式DRAM存储器的图形子系统。嵌入式DRAM存储器用作用于2-D图形加速器的帧缓冲存储器和/或临时存储存储器。嵌入式DRAM存储器还用作3-D图形加速器或外部中央处理单元（CPU）的高速缓冲存储器。嵌入式DRAM存储器在逻辑上被划分为多个独立存储体，从而导致相对较快的平均存储器周期时间。更具体地说，嵌入式DRAM存储器每个时钟周期处理一个事务，用于没有bank冲突的访问。任何事务的存储器访问时间（例如，银行冲突访问）不大于存储器周期时间加上存储器访问时间减1时钟周期。

34. 发明授权

US5787267A Caching method and circuit for a memory system with circuit module architecture 失效
标题翻译：具有电路模块架构的存储器系统的缓存方法和电路
公开(公告)号：US5787267A
公开(公告)日：1998-07-28
申请号：US479915
申请日：1995-06-07
申请人： Wingyu Leung , Kit Sang Tam
发明人： Wingyu Leung , Kit Sang Tam
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0893 , G06F12/084
摘要： A structure and method of implementing a cache memory for a multi-processor system. The cache memory includes a main memory which is coupled to a main memory bus. A plurality of processors can also be coupled to the main memory bus. The main memory includes a plurality of RAM circuit module memory banks. The sense amplifiers of a predetermined number of banks are used as cache memory (i.e., sense amplifier cache lines). The number of banks used with sense amplifiers activated is substantially less than the total number of banks. The banks which are not used as cache memory are kept in a precharged state.
摘要翻译：实现用于多处理器系统的高速缓冲存储器的结构和方法。高速缓冲存储器包括耦合到主存储器总线的主存储器。多个处理器也可以耦合到主存储器总线。主存储器包括多个RAM电路模块存储体。将预定数量的存储体的读出放大器用作高速缓冲存储器（即，读出放大器高速缓存行）。激活的读出放大器使用的存储体数量远远少于银行总数。不用作高速缓冲存储器的存储体保持在预充电状态。

35. 发明授权

US5729152A Termination circuits for reduced swing signal lines and methods for operating same 失效
标题翻译：用于减少摆动信号线的终端电路及其操作方法
公开(公告)号：US5729152A
公开(公告)日：1998-03-17
申请号：US549610
申请日：1995-10-27
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G11C11/41 , G06F3/00 , G06F12/16 , G06F13/16 , G06F13/40 , G11C7/00 , G11C11/401 , G11C11/407 , G11C11/417 , G11C29/00 , G11C29/04 , H04L25/02 , H03K17/16
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02B60/1228 , Y02B60/1235
摘要： A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The memory device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. The memory device includes a resynchronization circuit which allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation. Thus, each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.
摘要翻译：一种存储器件，其利用通过单向非对称信号摆幅（DASS）总线并联到主I / O模块的多个存储器模块。这种结构提供了一个在电源电压的一半左右，高输入，高数据带宽，短访问时间，低延迟和高抗噪声的对称摆动的I / O方案。存储器件利用改进的列存取电路，包括改进的地址排序电路和每个存储器模块内的数据放大器。存储器件包括再同步电路，其允许器件使用相同的引脚同步和异步地操作。每个存储器模块具有独立的地址和命令解码器，以实现独立操作。因此，只有当在特定存储器模块内执行存储器访问操作时，每个存储器模块才被DASS总线上的命令激活。存储器件包括用于替换有缺陷的存储器模块的冗余存储器模块。可以通过DASS总线上的命令进行更换。存储器件可被配置为将单个输入数据流同时写入多个存储器模块或执行高速交错读写操作。在一个实施例中，多个存储器件耦合到公共的高速I / O总线，而不需要存储器模块中的大的总线驱动器和复杂的总线接收器。

36. 发明授权

US5615169A Method and structure for controlling internal operations of a DRAM array 失效
标题翻译：用于控制DRAM阵列的内部操作的方法和结构
公开(公告)号：US5615169A
公开(公告)日：1997-03-25
申请号：US522032
申请日：1995-08-31
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C11/409 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4076 , G11C11/4096 , G11C7/22
摘要： A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a rising edge of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before the falling edge of the clock signal occurs. The falling edge is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before the subsequent rising edge of the clock signal. The subsequent rising edge is then used to initiate the column address decoding operation of the DRAM array. A test mode is included which allows the DRAM array to be operated asynchronously for testing purposes.
摘要翻译：响应于行访问（RAS＃）信号和时钟信号的上升沿和下降沿来控制对DRAM阵列的访问定时的方法和结构。当接收到行存取信号并且检测到时钟信号的上升沿时，行地址解码和均衡电路的去激活被启动。在时钟信号的下降沿发生之前，行地址解码和均衡电路的去激活完成。然后，下降沿用于启动DRAM阵列的读出放大器的导通。读出放大器在时钟信号的后续上升沿之前导通。随后的上升沿用于启动DRAM阵列的列地址解码操作。包括测试模式，允许DRAM阵列异步运行以进行测试。

37. 发明授权

US5498990A Reduced CMOS-swing clamping circuit for bus lines 失效
标题翻译：减少用于总线的CMOS摆幅钳位电路
公开(公告)号：US5498990A
公开(公告)日：1996-03-12
申请号：US417511
申请日：1995-04-05
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F5/16 , G06F11/00 , G06F11/10 , G06F11/20 , G06F12/06 , G06F13/40 , G11C29/00 , G11C29/48 , H01L21/66 , H01L27/02 , H04L25/02 , H03K5/08
CPC分类号： H04L25/026 , G06F12/0661 , G06F13/4077 , G06F5/16 , G11C29/006 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/832 , G11C29/88 , H01L22/22 , G06F11/006 , G06F11/10 , G06F11/1666 , H01L27/0203 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.
摘要翻译：具有通过I / O总线耦合到存储器控制器的几个存储器件的存储器系统，每个存储器件包括通过内部总线耦合到芯片I / O接口的多个存储器模块。该系统包括用于以减小的CMOS摆动驱动I / O总线的电路，用于在一个总线方向上以完全CMOS摆动驱动内部总线并且在另一个总线方向上以减小的CMOS摆幅驱动内部总线的电路列地址产生电路，用于允许在解码器延迟被消除的情况下访问顺序寻址的数据;以及电路，用于将来自源时钟的数据重新同步到具有降低的访问延迟代价的目的地时钟。同时将数据写入多个电路模块会显着增加存储器的写入带宽。还包括动态基地址映射到地址空间，跨多个存储器模块的读或写操作，新颖的I / O总线格式以及用于测试冗余存储器子阵列的协议和测试模式。

38. 发明授权

US5047979A High density SRAM circuit with ratio independent memory cells 失效
标题翻译：具有比例独立存储单元的高密度SRAM电路
公开(公告)号：US5047979A
公开(公告)日：1991-09-10
申请号：US538998
申请日：1990-06-15
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C11/412 , G11C11/419
CPC分类号： G11C11/419 , G11C11/412
摘要： Briefly, a high density, static, random access memory (SRAM) circuit with ratio independent memory cells employs a number (plurality) of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells of the present invention differs from corresponding, prior art type SRAM cells in that the SRAM cells of the present invention each include transistors of similar size (channel width).
摘要翻译：简而言之，具有比例独立存储单元的高密度，静态，随机存取存储器（SRAM）电路采用多个（4T-2R）或（6T）型SRAM单元和再生感测放大器。本发明的每个SRAM单元与相应的现有技术类型的SRAM单元的不同之处在于，本发明的SRAM单元各自包括类似尺寸的晶体管（沟道宽度）。

39. 发明授权

US09767914B1 Durable maintenance of memory cell electric current sense window following program-erase operations to a non-volatile memory 有权
公开(公告)号：US09767914B1
公开(公告)日：2017-09-19
申请号：US15289235
申请日：2016-10-10
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C16/04 , G11C16/34 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/08
CPC分类号： G11C16/16 , G11C16/10 , G11C16/3445 , G11C16/3459
摘要： A method of a state machine executing instructions related to program-erase operations performed on a non-volatile memory is disclosed. The method includes implementing a program-erase loop counter in the state machine, and presetting a threshold for an electric current of memory cells and a step time for each of the program and the erase operation. Based on repeatedly executing a number of comparison and verification operations, each for a duration of the preset step time until the program-erase loop counter reaches a maximum value thereof, the electric current of the each programmed-erased memory cell is maintained at a desired level thereof following termination of the each of the program and the erase operation.

40. 发明授权

US08489843B2 Configurable memory device 有权
标题翻译：可配置的存储设备
公开(公告)号：US08489843B2
公开(公告)日：2013-07-16
申请号：US12763240
申请日：2010-04-20
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0292 , G06F2212/205 , G06F2212/7201
摘要： A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.
摘要翻译：一种方法包括通过提供包括一个或多个非易失性存储器单元的非易失性存储器单元阵列和在衬底上包括一个或多个易失性存储器单元的易失性存储器单元的阵列来形成存储器件。该方法还包括通过与其相关联的一组寄存器适当地编程与存储器设备相关联的地址转换逻辑，以使与存储器设备的扇区相关联的地址的可配置映射与与该存储器设备相关联的计算系统中的任何存储器地址空间位置存储设备。地址转换逻辑被配置为使得能够将与存储器设备的扇区相关联的外部虚拟地址转换为与其相关联的物理地址。

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