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31. 发明授权

US5763305A Method for forming a semiconductor memory device with a capacitor 失效
标题翻译：用电容器形成半导体存储器件的方法
公开(公告)号：US5763305A
公开(公告)日：1998-06-09
申请号：US784298
申请日：1997-01-16
申请人： Fang-Ching Chao
发明人： Fang-Ching Chao
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S148/014
摘要： A method of fabricating a semiconductor memory device having a capacitor. First, a first insulating layer is formed on a substrate to cover the transistor. Next, a second insulating layer and a first conductive layer are formed in order. The first conductive layer only covers a portion of the second insulating layer to form a branch-like conductive layer. Then, a third insulating layer is formed. An opening is next formed. A second conductive layer is filled into the opening and therefore electrically connected to the source/drain region of the transistor to form a trunk-like conductive layer. Next, the second and the third insulating layers are removed. After a dielectric film is formed on the exposed surfaces of the first and second conductive layers, a third conductive layer is formed on the dielectric film to form an opposed electrode.
摘要翻译：一种制造具有电容器的半导体存储器件的方法。首先，在基板上形成第一绝缘层以覆盖晶体管。接下来，依次形成第二绝缘层和第一导电层。第一导电层仅覆盖第二绝缘层的一部分以形成分支状导电层。然后，形成第三绝缘层。接下来形成一个开口。第二导电层填充到开口中，因此电连接到晶体管的源极/漏极区域以形成树干状的导电层。接下来，去除第二和第三绝缘层。在第一和第二导电层的暴露表面上形成电介质膜之后，在该电介质膜上形成第三导电层以形成相对的电极。

32. 发明授权

US5739060A Method of fabricating a capacitor structure for a semiconductor memory device 失效
标题翻译：制造半导体存储器件的电容器结构的方法
公开(公告)号：US5739060A
公开(公告)日：1998-04-14
申请号：US735560
申请日：1996-10-23
申请人： Fang-Ching Chao
发明人： Fang-Ching Chao
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S148/014
摘要： A method of fabricating a semiconductor memory device having a transfer transistor and a storage capacitor. First, a first insulating layer is formed on the substrate to cover the transfer transistor. Next, a first conductive layer is formed, which penetrates the first insulating layer and is electrically connected to one of the source/drain regions of the transfer transistor. A pillar-shaped layer is formed on the first conductive layer. At least first and second films are successively formed on the first conductive layer and the pillar-shaped layer. Then, the second film, the first film, and the first conductive layer are patterned to form an opening, exposing the first insulating layer. A second conductive layer is then formed on sidewalls of the opening. The pillar-shaped layer and the first film are then removed. Finally, a dielectric layer is formed on the first and second conductive layers and the second film and a third conductive layer is formed on the dielectric layer.
摘要翻译：一种制造具有转移晶体管和存储电容器的半导体存储器件的方法。首先，在衬底上形成第一绝缘层以覆盖转移晶体管。接下来，形成第一导电层，其穿过第一绝缘层并电连接到转移晶体管的源/漏区之一。在第一导电层上形成柱状层。至少第一和第二膜依次形成在第一导电层和柱状层上。然后，将第二膜，第一膜和第一导电层图案化以形成开口，暴露第一绝缘层。然后在开口的侧壁上形成第二导电层。然后取出柱状层和第一膜。最后，在第一和第二导电层和第二膜上形成电介质层，在介电层上形成第三导电层。

33. 发明授权

US5633191A Process for minimizing encroachment effect of field isolation structure 失效
标题翻译：减少现场隔离结构侵扰效应的过程
公开(公告)号：US5633191A
公开(公告)日：1997-05-27
申请号：US699608
申请日：1996-08-19
申请人： Fang-Ching Chao
发明人： Fang-Ching Chao
IPC分类号： H01L21/32 , H01L21/76
CPC分类号： H01L21/32
摘要： A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a polysilicon layer is deposited on a laminate comprising a substrate having thereon a pad oxide, and the stacked layers on the pad oxide. An overhang layer is deposited on the polysilicon layer, and a photo-resist mask which masks the active regions is then applied so as to remove the unmasked overhang layer and the unmasked polysilicon layer. The resultant structure is isotropically etched to partially undercut the vertical portions of the polysilicon layer under the overhang layer so as to form an overhang. The photo-resist is stripped, and the stacked layers not covered by the overhang layer are etched anisotropically. The channel-stop ions are implanted, and the overhang layer is removed. Anisotropically etch the stacked layers by using the polysilicon layer as a mask, and then the resultant structure is subjected to oxidation to form the isolation regions. The channel stop region is self-aligned to the resultant field oxide and the isolation structure is free of the impurity encroachment effect.
摘要翻译：公开了一种用于最小化NMOS，PMOS和CMOS集成电路的场隔离结构的杂质侵入效应的方法。在该过程中，多晶硅层沉积在包括其上具有衬垫氧化物的衬底的叠层上，并且衬垫氧化物上的堆叠层。在多晶硅层上沉积悬垂层，然后施加掩蔽有源区的光致抗蚀剂掩模，以去除未掩蔽的悬垂层和未掩模的多晶硅层。所得到的结构被各向同性地蚀刻，以在突出层下方部分地切割多晶硅层的垂直部分，从而形成突出端。剥离光致抗蚀剂，并且不被悬垂层覆盖的堆叠层被各向异性地蚀刻。植入通道 - 停止离子，去除悬垂层。通过使用多晶硅层作为掩模对各堆叠层进行各向异性蚀刻，然后将所得结构进行氧化以形成隔离区。通道停止区域与得到的场氧化物自对准，隔离结构没有杂质侵入效应。

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