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31. 发明申请

US20220077315A1 TRANSISTOR STRUCTURE WITH METAL INTERCONNECTION DIRECTLY CONNECTING GATE AND DRAIN/SOURCE REGIONS 有权
公开(公告)号：US20220077315A1
公开(公告)日：2022-03-10
申请号：US17468683
申请日：2021-09-08
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu
IPC分类号： H01L29/78 , H01L27/088 , H01L29/10 , H01L29/06
摘要： A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

32. 发明申请

US20200335593A1 TRANSISTOR STRUCTURE WITH REDUCED LEAKAGE CURRENT AND ADJUSTABLE ON/OFF CURRENT 审中-公开
公开(公告)号：US20200335593A1
公开(公告)日：2020-10-22
申请号：US16847693
申请日：2020-04-14
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu , Li-Ping Huang
IPC分类号： H01L29/417 , H01L29/10 , H01L29/78
摘要： A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

33. 发明申请

US20200185388A1 UNIFIED MICRO SYSTEM WITH MEMORY IC AND LOGIC IC 审中-公开
公开(公告)号：US20200185388A1
公开(公告)日：2020-06-11
申请号：US16708442
申请日：2019-12-10
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu
IPC分类号： H01L27/108 , H01L25/065 , H01L27/06 , G11C5/02
摘要： An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

34. 发明申请

US20200168736A1 REDUCED-FORM-FACTOR TRANSISTOR WITH SELF-ALIGNED TERMINALS AND ADJUSTABLE ON/OFF-CURRENTS AND MANUFACTURE METHOD THEREOF 审中-公开
公开(公告)号：US20200168736A1
公开(公告)日：2020-05-28
申请号：US16388836
申请日：2019-04-18
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu
IPC分类号： H01L29/78 , H01L29/40 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/66 , H01L21/762 , H01L21/02 , H01L29/417
摘要： A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.

35. 发明授权

US09748002B2 System-in-package module with memory 有权
公开(公告)号：US09748002B2
公开(公告)日：2017-08-29
申请号：US14522567
申请日：2014-10-23
申请人： Etron Technology, Inc.
发明人： Weng-Dah Ken , Chao-Chun Lu
IPC分类号： G11C29/02 , H01L25/18 , G06F11/10 , G11C5/04 , G11C11/00 , G11C29/52 , H01L23/00 , H01L23/31 , H01L25/065 , H01L25/10
CPC分类号： G11C29/023 , G06F11/106 , G06F11/1064 , G11C5/04 , G11C11/005 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/81193 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.

36. 发明申请

US20160029009A1 ATTACHABLE THREE-DIMENSIONAL SCAN MODULE 有权
标题翻译：可连接的三维扫描模块
公开(公告)号：US20160029009A1
公开(公告)日：2016-01-28
申请号：US14807903
申请日：2015-07-24
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu , Le-Shan Hsueh , Wen-Kuo Lin
IPC分类号： H04N13/02 , G06T5/20
CPC分类号： H04N13/296 , G01B5/0004 , G01B11/2545 , G01B21/042 , G06T5/20 , H04N13/239 , H04N13/246 , H04N13/271 , H04N2013/0077 , H04N2013/0081
摘要： An attachable three-dimensional scan module includes an attachable unit, at least two image sensing units, a depth map generation unit, and an output interface. The attachable unit fixes the attachable three-dimensional scan module on a mobile device. When the mobile device is moved around an object, a first image sensing unit and a second image sensing unit of the at least two image sensing units capture a plurality of first images including the object and a plurality of second images including the object, respectively. A plurality of depth maps generated by the depth map generation unit, the plurality of first images, and the plurality of second images are used for generating a color three-dimensional scan result corresponding to the object. The output interface outputs the color three-dimensional scan result, or the plurality of first images, the plurality of second images, and the plurality of depth maps.
摘要翻译：可附接的三维扫描模块包括可附接单元，至少两个图像感测单元，深度图生成单元和输出接口。可附接单元将可附接的三维扫描模块固定在移动设备上。当移动设备围绕物体移动时，所述至少两个图像感测单元的第一图像感测单元和第二图像感测单元分别捕获包括对象的多个第一图像和包括对象的多个第二图像。由深度图生成单元，多个第一图像和多个第二图像生成的多个深度图用于生成与该对象对应的彩色三维扫描结果。输出接口输出彩色三维扫描结果或多个第一图像，多个第二图像和多个深度图。

37. 发明申请

US20150326048A1 CHARGE FARE METER 审中-公开
标题翻译：收费表
公开(公告)号：US20150326048A1
公开(公告)日：2015-11-12
申请号：US14705959
申请日：2015-05-06
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu
IPC分类号： H02J7/00 , G06Q30/04 , G06Q50/06 , H02J7/02
CPC分类号： G06Q30/04 , G06Q50/06 , H02J7/0047 , H02J7/0052 , H02J50/00 , H02J50/10 , H02J50/80 , Y04S10/54
摘要： A charge fare meter includes a charge module and a display. The charge module is used for outputting a direct (DC) current and calculating total charges, wherein the charge module includes an input interface, a calculating unit, and an output interface. The input interface is used for converting power provided by an alternating current power source or the DC power source into the DC current. The calculating unit is electrically connected to the input interface for calculating the total charges. The output interface is electrically connected to the calculating unit for outputting the DC current. The display is electrically connected to the charge module for displaying the DC current, a voltage corresponding to the DC current, or a charge fare corresponding to the total charges.
摘要翻译：收费费用表包括充电模块和显示器。充电模块用于输出直流（DC）电流并计算总电荷，其中充电模块包括输入接口，计算单元和输出接口。输入接口用于将由交流电源或直流电源提供的电力转换成直流电流。计算单元电连接到输入接口以计算总电荷。输出接口电连接到用于输出直流电流的计算单元。显示器电连接到充电模块，用于显示DC电流，对应于DC电流的电压或对应于总电荷的充电费。

38. 发明申请

US20150317276A1 RECONFIGURABLE HIGH SPEED MEMORY CHIP MODULE AND ELECTRONIC DEVICE WITH A RECONFIGURABLE HIGH SPEED MEMORY CHIP MODULE 有权
标题翻译：具有可重新配置的高速存储芯片模块的可重新配置的高速存储芯片模块和电子设备
公开(公告)号：US20150317276A1
公开(公告)日：2015-11-05
申请号：US14800682
申请日：2015-07-15
申请人： Etron Technology, Inc.
发明人： Weng-Dah Ken , Chao-Chun Lu , Jan-Mye Sung
IPC分类号： G06F13/42 , G11C8/18 , G11C5/06
CPC分类号： G06F13/4234 , G06F13/4018 , G06F13/42 , G11C5/06 , G11C8/18 , H01L23/544 , H01L23/585 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15311 , H01L2924/3025 , Y02D10/14 , Y02D10/151 , H01L2924/00
摘要： A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.
摘要翻译：可重新配置的高速存储器芯片模块包括一种存储单元阵列组，第一传输总线和逻辑单元。该型存储单元阵列组包括多个存储单元阵列集成电路（IC）。耦合到型存储单元阵列组的第一传输总线具有第一可编程发送或接收数据速率，第一可编程发送或接收信号摆幅，第一可编程总线宽度及其组合。逻辑单元耦合到第一传输总线，用于通过第一传输总线访问类型存储单元阵列组。

39. 发明授权

US11869972B2 Reduced-form-factor transistor with self-aligned terminals and adjustable on/off-currents and manufacture method thereof 有权
公开(公告)号：US11869972B2
公开(公告)日：2024-01-09
申请号：US16388836
申请日：2019-04-18
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu
IPC分类号： H01L29/78 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/66 , H01L21/762 , H01L21/02 , H01L29/417 , H01L29/40 , H01L21/3213 , H01L21/265 , H01L29/49 , H01L21/311
CPC分类号： H01L29/7851 , H01L21/0262 , H01L21/02532 , H01L21/02598 , H01L21/02636 , H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/401 , H01L29/41783 , H01L29/6656 , H01L29/66795 , H01L21/0228 , H01L21/26513 , H01L21/31111 , H01L21/32133 , H01L29/4933
摘要： A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.

40. 发明授权

US11825645B2 Memory cell structure 有权
公开(公告)号：US11825645B2
公开(公告)日：2023-11-21
申请号：US17337391
申请日：2021-06-02
申请人： Etron Technology, Inc.
发明人： Chao-Chun Lu
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/0335 , H10B12/053 , H10B12/34 , H10B12/482
摘要： The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

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