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31. 发明授权

US06936909B2 Gate dielectric antifuse circuit to protect a high-voltage transistor 有权
标题翻译：栅介质反熔丝电路保护高压晶体管
公开(公告)号：US06936909B2
公开(公告)日：2005-08-30
申请号：US10230928
申请日：2002-08-29
申请人： Kenneth W. Marr , John D. Porter
发明人： Kenneth W. Marr , John D. Porter
IPC分类号： G11C17/18 , H01L23/525 , H01L29/78 , H01L29/00 , H01L29/01 , H01L31/036
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/0248 , H01L29/0847 , H01L29/1045 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.
摘要翻译：根据本发明的实施例，电路具有用于保护栅介质反熔丝电路中的高压晶体管的元件。反熔丝在耦合以接收升高电压的第一端子和第二端子之间具有栅极电介质层，并且高压晶体管耦合到反熔丝并具有栅极端子。电源电压和升高电压之间的中间电压耦合到高电压晶体管的栅极端子，以保护高压晶体管。

32. 发明授权

US06847198B2 Frequency sensing voltage regulator 有权
标题翻译：频率感应电压调节器
公开(公告)号：US06847198B2
公开(公告)日：2005-01-25
申请号：US10443043
申请日：2003-05-22
申请人： Kent M. Kalpakjian , John D. Porter
发明人： Kent M. Kalpakjian , John D. Porter
IPC分类号： G05F1/46 , G05F1/44 , G05F1/40
CPC分类号： G05F1/466
摘要： A frequency sensing voltage regulator is disclosed. A source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a switching transistor, and a source connected to a load. The gate of the switching transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the switching transistor, the amount of current produced by the source follower transistor is made a function of the cycle rate of the system clock and the current provided by the source follower transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.
摘要翻译：公开了一种频率感测电压调节器。源极跟随器晶体管具有连接到预定栅极电压的栅极，通过开关晶体管耦合到外部电源电压的漏极和连接到负载的源极。开关晶体管的栅极由延迟电路控制，通过该延迟电路从系统时钟导出的脉冲通过。通过使用延迟电路和开关晶体管，由源极跟随器晶体管产生的电流量作为系统时钟的周期速率的函数，并且由源极跟随器晶体管提供的电流跟踪频率相关的电流要求的负载，导致在宽电流范围内电源电压Vcc的变化减小。

33. 发明授权

US06751150B2 Circuits and method to protect a gate dielectric antifuse 有权
标题翻译：保护栅极电介质反熔丝的电路和方法
公开(公告)号：US06751150B2
公开(公告)日：2004-06-15
申请号：US10231756
申请日：2002-08-29
申请人： Kenneth W. Marr , John D. Porter
发明人： Kenneth W. Marr , John D. Porter
IPC分类号： G11C700
CPC分类号： G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.
摘要翻译：根据本发明的实施例，通过将提升的电压耦合到反熔丝的第一端子来操作反熔丝电路，通过耦合到反熔丝的第二端子的编程驱动器电路来控制反熔丝中的电流，反熔丝与耦合在反熔丝的第一端子和程序驱动电路之间的旁路电路以保护反熔丝。反熔丝包括在第一端子和第二端子之间的栅极电介质层。本发明的实施例保护栅极绝缘反熔丝。

34. 发明授权

US06657512B2 Method to find a value within a range using weighted subranges 有权
公开(公告)号：US06657512B2
公开(公告)日：2003-12-02
申请号：US10277866
申请日：2002-10-22
申请人： William N. Thompson , John D. Porter , Larren Gene Weber
发明人： William N. Thompson , John D. Porter , Larren Gene Weber
IPC分类号： H03H1130
CPC分类号： G11C7/1051 , G11C7/1069 , H03H7/40 , H03H11/245 , H03H11/28 , H03H17/0263
摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

35. 发明授权

US06529421B1 SRAM array with temperature-compensated threshold voltage 有权
公开(公告)号：US06529421B1
公开(公告)日：2003-03-04
申请号：US09940968
申请日：2001-08-28
申请人： Kenneth W. Marr , John D. Porter
发明人： Kenneth W. Marr , John D. Porter
IPC分类号： G11C1604
CPC分类号： G11C11/412 , G11C5/147 , G11C11/417
摘要： Systems and methods are provided for a temperature-compensated threshold voltage VT. The stability problems associated with temperature changes are reduced for LL4TCMOS SRAM cells by providing a temperature-compensated VTN. According to one embodiment, a temperature-based modulation of a VBB potential back-biases a triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated VTN that is flat or relatively flat with respect to temperature. One embodiment provides a bias generator, including a charge pump coupled to a body terminal of the transistor(s), and a comparator coupled to the charge pump. The comparator includes a first input that receives a reference voltage, a second input that receives a VT-dependent voltage, and an output that presents a control signal to the charge pump and causes the charge pump to selectively charge the body terminal of the transistor to compensate for temperature changes.

36. 发明授权

US06301188B1 Method and apparatus for registering free flow information 有权
标题翻译：注册自由流量信息的方法和装置
公开(公告)号：US06301188B1
公开(公告)日：2001-10-09
申请号：US09372245
申请日：1999-08-11
申请人： Larren G. Weber , William N. Thompson , John D. Porter
发明人： Larren G. Weber , William N. Thompson , John D. Porter
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/225
摘要： A synchronous circuit, such as an SRAM, includes core circuitry for processing input signals and multiple terminals for receiving, respectively, an input signal, an external clock signal and a control signal. The synchronous circuit includes a latch for receiving the input signal and an internal clock signal. The latch has an output connected to the core circuitry and can operate in a latched state and an unlatched state. The circuit also includes an internal clock controller for receiving the external clock signal and the control signal and for providing the internal clock signal to the latch to control transitions of the latch between the latched and unlatched states based on the external clock signal and the control signal. The internal clock controller extends the period of time in which the latch operates in the latched state in response to an input from the external clock, and maintains the latch in the latched state for multiple cycles of the external clock in response to assertion of the control signal.
摘要翻译：诸如SRAM的同步电路包括用于处理输入信号的核心电路和用于分别接收输入信号，外部时钟信号和控制信号的多个端子。同步电路包括用于接收输入信号和内部时钟信号的锁存器。闩锁具有连接到核心电路的输出并且可以在锁定状态和解锁状态下操作。电路还包括内部时钟控制器，用于接收外部时钟信号和控制信号，并且用于将内部时钟信号提供给锁存器，以基于外部时钟信号和控制信号来控制锁存状态和解锁状态之间的锁存器的转换。内部时钟控制器响应于来自外部时钟的输入而延长锁存器在锁存状态下操作的时间段，并且响应于控制的断言将锁存器保持在锁存状态多个外部时钟周期信号。

37. 发明授权

US06292407B1 Method and apparatus for circuit variable updates 有权
标题翻译：电路变量更新方法和装置
公开(公告)号：US06292407B1
公开(公告)日：2001-09-18
申请号：US09416301
申请日：1999-10-12
申请人： John D. Porter , Larren Gene Weber
发明人： John D. Porter , Larren Gene Weber
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106
摘要： Improved methods and structures are provided that allow for the updating of output driver impedances for a circuit to match an impedance of the transmission line to which the circuit is coupled. In particular, improved methods and structures are provided which allow for a reliable updating of the output driver impedance without requiring the output driver to be tristated in order to prevent data loss. Embodiments of a method of forming an integrated circuit include coupling a data line to an enable input of a holding device. The method also includes coupling at least one impedance line to a data input of the holding device. The at least one impedance line carries an impedance update signal. Further, an impedance of the data line at a data output of the memory device is capable of being updated to a value equal to the impedance update signal when the data line is quiescent. The present invention also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application.
摘要翻译：提供了改进的方法和结构，其允许更新电路的输出驱动器阻抗以匹配电路耦合到的传输线的阻抗。特别地，提供了改进的方法和结构，其允许可靠地更新输出驱动器阻抗，而不需要三态输出驱动器以防止数据丢失。形成集成电路的方法的实施例包括将数据线耦合到保持装置的使能输入。该方法还包括将至少一个阻抗线耦合到保持装置的数据输入端。所述至少一个阻抗线承载阻抗更新信号。此外，当数据线静止时，存储器件的数据输出处的数据线的阻抗能够被更新为等于阻抗更新信号的值。本发明还包括结构以及结合这样的结构的系统，其全部根据本申请中提供的方法形成。

38. 发明授权

US06275119B1 Method to find a value within a range using weighted subranges 有权
标题翻译：使用加权子范围查找范围内的值的方法
公开(公告)号：US06275119B1
公开(公告)日：2001-08-14
申请号：US09382525
申请日：1999-08-25
申请人： William N. Thompson , John D. Porter , Larren Gene Weber
发明人： William N. Thompson , John D. Porter , Larren Gene Weber
IPC分类号： H03H1130
CPC分类号： G11C7/1051 , G11C7/1069 , H03H7/40 , H03H11/245 , H03H11/28 , H03H17/0263
摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.
摘要翻译：公开了一种从值范围内找到未知值的方法，其将范围划分为加权子范围，然后从范围内的任意搜索值开始执行多个简单比较，以确定每个子范围的值，导致与目标值匹配。该方法还可以检测目标值在范围之外的情况。在一个实施例中，将在值范围内找到未知值的方法应用于阻抗匹配。在本实施例中，集成电路上的引脚的输出阻抗与连接到其的负载的阻抗自动匹配。输出驱动器具有可控阻抗，可以在特定阻抗范围内进行调节，以匹配驱动的外部负载阻抗。

39. 发明授权

US6005797A Latch-up prevention for memory cells 失效
标题翻译：记忆细胞的锁定预防
公开(公告)号：US6005797A
公开(公告)日：1999-12-21
申请号：US45465
申请日：1998-03-20
申请人： John D. Porter , William N. Thompson
发明人： John D. Porter , William N. Thompson
IPC分类号： G11C11/412 , H01L27/11 , G11C11/00 , H01L29/76
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V.sub.cc through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.
摘要翻译：提供具有一对交叉耦合CMOS反相器的SRAM存储单元。形成每个CMOS反相器的上拉晶体管的源极通过其中形成各自的衬底的寄生电阻耦合到Vcc。因此，p型上拉晶体管的源极总是处于小于或等于N阱的电位的电位，使得寄生PNP晶体管的发射极 - 基极结不能变为正向偏置，并且闭锁不能发生。

40. 发明授权

US5717342A Output buffer incorporating shared intermediate nodes 失效
标题翻译：包含共享中间节点的输出缓冲区
公开(公告)号：US5717342A
公开(公告)日：1998-02-10
申请号：US745410
申请日：1996-11-22
申请人： Younes J. Lotfi , John D. Porter
发明人： Younes J. Lotfi , John D. Porter
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361
摘要： An output buffer is disclosed for an integrated circuit having a varying number of simultaneously switching outputs. As fewer outputs on the integrated circuit are simultaneously switching, the output conductance of certain logic gates within each of the output buffers on the integrated circuit is increased by sharing intermediate nodes between each of the output buffers. Consequently, the speed of the output buffer increases as fewer of the outputs simultaneously switch and internally generated noise is small. Conversely, as additional outputs simultaneously switch, the output conductance of certain logic gates within the output buffer is decreased, resulting in reduced speed of the output buffers and a corresponding reduction in internally generated noise.
摘要翻译：公开了一种具有不同数量的同时开关输出的集成电路的输出缓冲器。随着集成电路中的较少输出同时切换，通过在每个输出缓冲器之间共享中间节点来增加集成电路中每个输出缓冲器内的某些逻辑门的输出电导。因此，输出缓冲器的速度随着输出同时切换和内部产生的噪声较小而增加。相反，随着额外的输出同时切换，输出缓冲器内某些逻辑门的输出电导减小，导致输出缓冲器的速度降低，内部产生的噪声相应减少。

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