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31. 发明申请

US20050116293A1 Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate 有权
标题翻译：晶体管结构，存储单元，DRAM以及在半导体衬底中制造晶体管结构的方法
公开(公告)号：US20050116293A1
公开(公告)日：2005-06-02
申请号：US10975085
申请日：2004-10-28
申请人： Matthias Goldbach , Ulrich Frey , Bjorn Fischer
发明人： Matthias Goldbach , Ulrich Frey , Bjorn Fischer
IPC分类号： H01L21/336 , H01L21/8242 , H01L29/423 , H01L27/01
CPC分类号： H01L27/10888 , H01L27/10855 , H01L27/10867 , H01L27/10873 , H01L29/42368
摘要： Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.
摘要翻译：晶体管结构，具有连接到待绝缘的电荷存储装置的一个源极/漏极区域包括非对称栅极导体结构。在面向一个源极/漏极区域的第一侧壁处，不对称栅极导体结构具有较大厚度的侧壁氧化物和具有比相对的第二侧壁长的长度的鸟嘴结构。对于栅极导体结构的相同特征尺寸，有效沟道长度增加。可以以更高的密度实现存储单元。

32. 发明授权

US06878600B2 Method for fabricating trench capacitors and semiconductor device with trench capacitors 失效
标题翻译：制造沟槽电容器的方法和具有沟槽电容器的半导体器件
公开(公告)号：US06878600B2
公开(公告)日：2005-04-12
申请号：US10436426
申请日：2003-05-12
申请人： Albert Birner , Matthias Goldbach , Martin Franosch
发明人： Albert Birner , Matthias Goldbach , Martin Franosch
IPC分类号： H01L21/3063 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/1087
摘要： A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.
摘要翻译：一种用于制造具有中孔的沟槽的沟槽电容器的方法，所述沟槽电容器适用于分立电容器和集成半导体存储器，显着增加了电容器的电极的表面积，并因此显着增加了其电容。电化学地制造直径为约2〜50nm的小木蛾孔状通道的中孔。因此，可以产生具有大的电容容积比的电容。当介孔达到与另一个中孔或相邻沟槽的最小距离（自钝化）时，介孔的生长最终停止。因此，可以以自我调节的方式避免在两个相邻介孔之间形成“短路”。此外，提供一种半导体器件，其包括通过根据本发明的方法制造的半导体衬底的前侧上的至少一个沟槽电容器。

33. 发明授权

US08876019B2 Cleaning device for a lens of a headlight of a motor vehicle 有权
标题翻译：机动车头灯的镜头清洁装置
公开(公告)号：US08876019B2
公开(公告)日：2014-11-04
申请号：US11993183
申请日：2006-06-13
申请人： Thomas Discher , Matthias Goldbach , Uwe Martin , Rolf-Dieter Schlein , Annegret Kuech
发明人： Thomas Discher , Matthias Goldbach , Theo Kuech , Uwe Martin , Rolf-Dieter Schlein
IPC分类号： B05B1/10 , B60S1/46 , B05B1/30 , B05B15/10 , B60S1/52
CPC分类号： B60S1/528
摘要： A cleaning device (1) for a lens (2) of a headlight of a motor vehicle has two telescoping tubes (6, 7), the outer tube (6) holding a spray nozzle (9). The outer tube (6) is also surrounded by a protective tube (8) to be fixed in the motor vehicle. When the outer tube (6) is pulled out (9), the spray nozzle is displaced over the lens (2). The connections of the tubes (6, 7) are reliably protected from dirt accumulation.
摘要翻译：用于机动车辆前灯的透镜（2）的清洁装置（1）具有两个伸缩管（6,7），外管（6）保持喷嘴（9）。外管（6）也被保护管（8）包围，以固定在机动车辆中。当外管（6）被拉出（9）时，喷嘴在镜片（2）上移动。可靠地保护管（6,7）的连接免受污垢积聚。

34. 发明申请

US20130137234A1 METHODS FOR FORMING SEMICONDUCTOR DEVICES 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20130137234A1
公开(公告)日：2013-05-30
申请号：US13306702
申请日：2011-11-29
申请人： Peter Baars , Matthias Goldbach
发明人： Peter Baars , Matthias Goldbach
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/823821 , H01L21/31111 , H01L21/31116 , H01L21/31155 , H01L29/66545
摘要： Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.
摘要翻译：提供了形成半导体器件的方法。一种方法包括将沟槽蚀刻到硅衬底中并用绝缘材料填充沟槽以描绘多个间隔开的硅片。形成虚拟门结构，其包括覆盖并横向翅片的第一虚拟栅极结构。背面填充材料填充在虚拟栅极结构之间。去除第一伪栅极结构和绝缘材料的上部以暴露鳍片的活动鳍片部分。主动翅片部分被尺寸修改以形成改变的活动翅片部分。高k电介质材料和功函数确定栅电极材料沉积在改变的活性鳍片部分上。

35. 发明授权

US07378321B2 Method for patterning a semiconductor component 失效
标题翻译：图案化半导体部件的方法
公开(公告)号：US07378321B2
公开(公告)日：2008-05-27
申请号：US11392523
申请日：2006-03-29
申请人： Matthias Goldbach
发明人： Matthias Goldbach
IPC分类号： H01L21/336
CPC分类号： H01L27/10867
摘要： In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate. The first region is different from the second region. The first cover layer is patterned using a photolithographic mask so that the first region is uncovered and the second region remains covered by the first cover layer. The first region is uncovered, a second cover layer is applied to the uncovered first region, and the first cover layer is removed so that the second region is uncovered. The uncovered second region is then doped.
摘要翻译：在半导体部件图案化的方法中，第一覆盖层被施加到半导体衬底中的第一区域和半导体器件的第二区域。第一个区域与第二个区域不同。使用光刻掩模对第一覆盖层进行图案化，使得第一区域未被覆盖，并且第二区域保持被第一覆盖层覆盖。未覆盖第一区域，将第二覆盖层施加到未覆盖的第一区域，并且移除第一覆盖层，使得第二区域未被覆盖。然后掺杂未覆盖的第二区域。

36. 发明申请

US20070281416A1 Manufacturing method for an integrated semiconductor structure 失效
标题翻译：集成半导体结构的制造方法
公开(公告)号：US20070281416A1
公开(公告)日：2007-12-06
申请号：US11443602
申请日：2006-05-31
申请人： Peter Baars , Klaus Muemmler , Matthias Goldbach
发明人： Peter Baars , Klaus Muemmler , Matthias Goldbach
IPC分类号： H01L21/8244
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10811 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L27/10897
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.
摘要翻译：本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在存储单元区域中具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔; 在所述存储单元区域和外围设备区域上沉积第一保护层; 将所述至少一个栅极堆叠的所述盖暴露在所述外围设备区域中; 在处理步骤中修改所述外围设备区域中的所述至少一个栅极堆叠的所述暴露的盖，其中所述第一保护层用作所述存储单元区域中的掩模; 在所述外围设备区域中的所述修改的盖上形成第二保护层; 部分地去除所述第一和第二保护层，以便使所述第一和第二保护层大致相同的上层; 从所述第一接触孔去除所述第一保护层; 在所述外围设备区域中形成至少另一个接触孔，所述至少另一个接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或所述栅极叠层中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少另一个接触孔。

37. 发明授权

US07268037B2 Method for fabricating microchips using metal oxide masks 有权
标题翻译：使用金属氧化物掩模制造微芯片的方法
公开(公告)号：US07268037B2
公开(公告)日：2007-09-11
申请号：US11040091
申请日：2005-01-24
申请人： Stefan Jakschik , Thomas Hecht , Uwe Schröder , Matthias Goldbach
发明人： Stefan Jakschik , Thomas Hecht , Uwe Schröder , Matthias Goldbach
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/31111 , H01L21/3141 , H01L21/31616 , H01L29/66181
摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.
摘要翻译：用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。最后，再次选择性地除去氧化铝，例如使用热磷酸。由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。

38. 发明申请

US20070034927A1 Trench storage capacitor 审中-公开
标题翻译：沟槽存储电容
公开(公告)号：US20070034927A1
公开(公告)日：2007-02-15
申请号：US11272038
申请日：2005-11-14
申请人： Harald Seidl , Dirk Manger , Matthias Goldbach , Albert Birner , Stefan Slesazeck
发明人： Harald Seidl , Dirk Manger , Matthias Goldbach , Albert Birner , Stefan Slesazeck
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/945
摘要： A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a “buried” collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.
摘要翻译：沟槽存储电容器包括一掩埋板，其被掺杂的硅层延伸到芯套绝缘层的正上方。沟槽存储电容器的导体层优选地应用于“埋入”的轴环绝缘层，并借助于由ALD制成的保护层进行掩模。在示例性实施例中，导体层由非晶硅组成，其被用作下沟槽区域中的HSG层。

39. 发明授权

US07084043B2 Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor 失效
标题翻译：用于形成SOI衬底，垂直晶体管和具有垂直晶体管的存储单元的方法
公开(公告)号：US07084043B2
公开(公告)日：2006-08-01
申请号：US10792691
申请日：2004-03-05
申请人： Albert Birner , Steffen Breuer , Matthias Goldbach , Joern Luetzen , Dirk Schumann
发明人： Albert Birner , Steffen Breuer , Matthias Goldbach , Joern Luetzen , Dirk Schumann
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/1203
摘要： A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.
摘要翻译：在任何期望的几何形状的硅表面上制造绝缘体上硅层结构的方法可以局部地产生绝缘体上硅结构。该方法包括在硅表面区域形成中孔，中孔表面的氧化形成硅单晶的硅氧化物和肋状区域; 以及执行选择性外延工艺，其中硅在相对于氧化硅区域选择性地在未覆盖的肋区域上生长。肋区域保持在相邻的中孔之间的适当位置，一旦达到肋区域的预定的最小硅壁厚度，则该步骤结束，肋区域的露出，其布置在远离半导体衬底的相邻介孔之间的端部。该方法可用于制造具有这种类型的选择晶体管的垂直晶体管和存储单元。

40. 发明授权

US07049241B2 Method for forming a trench in a layer or a layer stack on a semiconductor wafer 有权
标题翻译：在半导体晶片上的层或层叠中形成沟槽的方法
公开(公告)号：US07049241B2
公开(公告)日：2006-05-23
申请号：US10937099
申请日：2004-09-08
申请人： Uwe Paul Schroeder , Matthias Goldbach , Tobias Mono
发明人： Uwe Paul Schroeder , Matthias Goldbach , Tobias Mono
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/11568 , H01L21/0274 , H01L21/0337 , H01L21/3086 , Y10S438/924
摘要： Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102–104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102–104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42). As a result, it is possible to form a trench (26) in the hard mask layer (12) and in the layer/layer stack (102–104) the width (52) of which trench is smaller than the lithographic resolution limit during the lithographic patterning of the resist (16).
摘要翻译：优选使用正性抗蚀剂，在施加在硬掩模层（12）上方的半导体晶片（1）上的光敏抗蚀剂（16）中形成抗蚀剂脊（20）。抗蚀剂脊（20）用作随后的注入步骤（46）的掩模。这利用了可以相对于植入部分（121）选择性地蚀刻出由抗蚀剂脊（20）遮蔽的部分（122）中的硬掩模层（12）的材料的效果。因此，图案化的硬掩模层相对于实际上被图案化的下层或层叠（102-104）用作蚀刻掩模。从形成为光敏抗蚀剂（16）中的线的抗蚀剂脊（10）以一种音调反转形式，在硬掩模层中形成有开口（24），并且已经形成了沟槽（26）形成在层/层堆叠（102-104）中。根据本发明，通过将抗蚀剂脊（20）暴露于氧等离子体（42）来减小抗蚀剂脊（20）的宽度（51,52）。结果，可以在硬掩模层（12）和层/层堆叠（102-104）中形成沟槽（26），其中沟槽的宽度（52）小于光刻分辨率极限抗蚀剂（16）的平版印刷图案化。

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