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    • 36. 发明授权
    • Array substrate and method for manufacturing the array substrate
    • 阵列基板和阵列基板的制造方法
    • US08298877B2
    • 2012-10-30
    • US12777347
    • 2010-05-11
    • Shin-Il ChoiSang-Gab KimYu-Gwang JeongHong-Kee Chin
    • Shin-Il ChoiSang-Gab KimYu-Gwang JeongHong-Kee Chin
    • H01L21/44H01L21/84
    • H01L27/124H01L27/1214H01L27/1288H01L29/42384H01L29/78696
    • An array substrate including: a gate electrode and a gate insulation layer disposed on a base substrate, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin-film transistor patterns.
    • 一种阵列基板,包括:栅极电极和栅极绝缘层,其设置在基底基板上,所述栅极绝缘层在第一区域具有第一厚度,在第二区域具有第二厚度,所述第一厚度大于所述第二厚度; 所述半导体图案设置在所述第一区域中的所述栅极绝缘层上,所述半导体图案的端部相对于所述栅极绝缘层具有阶梯部分; 设置在所述半导体图案上的欧姆接触图案,所述欧姆接触图案的与沟道部分相对的端部与所述半导体图案的端部对准; 以及设置在欧姆接触图案上的源极和漏极,源极和漏极彼此间隔开并且包括第一和第二薄膜晶体管图案。