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    • 39. 发明授权
    • Method of generating a prosodic model for adjusting speech style and apparatus and method of synthesizing conversational speech using the same
    • 生成用于调整语音风格的韵律模型的方法和使用其的合成对话语音的装置和方法
    • US07792673B2
    • 2010-09-07
    • US11593852
    • 2006-11-07
    • Seung Shin OhSang Hun KimYoung Jik Lee
    • Seung Shin OhSang Hun KimYoung Jik Lee
    • G10L13/06G10L13/08
    • G10L13/033G10L13/04
    • An apparatus and method for adjusting the friendliness of a synthesized speech and thus generating synthesized speech of various styles in a speech synthesis system are provided. The method includes the steps of defining at least two friendliness levels; storing recorded speech data of sentences, the sentences being made up according to each of the friendliness levels; extracting at least one of prosodic characteristics for each of the friendliness levels from the recorded speech data, said prosodic characteristics including at least one of a sentence-final intonation type, boundary intonation types of intonation phrases in the sentence, and an average value of F0 of the sentence, with respect to the recorded speech data; and generating a prosodic model for each of the friendliness levels by statistically modeling the at least one of the prosodic characteristics.
    • 提供了一种用于调整合成语音的友好性并因此在语音合成系统中生成各种风格的合成语音的装置和方法。 该方法包括以下步骤:定义至少两个友好级别; 存储句子的记录语音数据,根据每个友好级别构成句子; 从记录的语音数据中提取每个友好级别的韵律特征中的至少一个,所述韵律特征包括句子最终语调类型,句子中的语调短语的边界语调类型和平均值F0 相对于记录的语音数据; 以及通过对所述韵律特征中的至少一个进行统计学建模来为每个友善度级别生成韵律模型。
    • 40. 发明授权
    • SiGe semiconductor device and method of manufacturing the same
    • SiGe半导体器件及其制造方法
    • US07666749B2
    • 2010-02-23
    • US11947098
    • 2007-11-29
    • Sang Hun KimHyun Cheol BaeSang Heung Lee
    • Sang Hun KimHyun Cheol BaeSang Heung Lee
    • H01L21/331H01L21/8222
    • H01L29/7378H01L29/0821H01L29/66242
    • Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active region and a collector electrode region by forming a Si epitaxial layer on the substrate having the buried collector; forming an isolation layer on the substrate and exposing the collector layer and the collector electrode region; forming a collector pad oxide layer on the collector electrode region; stacking a base epitaxial layer and a pad oxide layer on the substrate having the collector pad oxide layer and patterning the pad oxide layer; forming a first polycrystalline Si (poly-Si) layer on the patterned pad oxide layer; exposing at least a portion of the patterned pad oxide layer by etching the first poly-Si layer; depositing a metal layer on the first poly-Si layer to form a first silicide layer; forming an oxide layer on the substrate having the first silicide layer, and exposing a base-emitter junction and the collector electrode region; forming an emitter electrode and a collector electrode by depositing a second poly-Si layer on the exposed base-emitter junction and collector electrode region; and depositing a metal layer on the emitter and collector electrodes to form a second silicide layer, and forming a base terminal, an emitter terminal, and a collector terminal. In this method, base parasitic resistance can be reduced, an electrical short due to agglomeration caused by Ge can be prevented during the formation of the silicide layer, and the base-emitter junction can be protected using the pad oxide layer from external processes, thereby enhancing process stability and reliability.
    • 提供了一种SiGe半导体器件及其制造方法。 该方法包括以下步骤:通过将杂质离子掺杂到形成在衬底上的掩埋集电区中来形成掩埋集电极; 通过在具有该埋设集电体的基板上形成Si外延层,形成作为有源区和集电极区的集电极层; 在所述基板上形成隔离层并使所述集电极层和所述集电极区域露出; 在集电极区域上形成集电极氧化层; 在具有集电极衬垫氧化物层的衬底上堆叠基极外延层和焊盘氧化物层,并对衬垫氧化物层进行构图; 在所述图案化衬垫氧化物层上形成第一多晶Si(多晶硅)层; 通过蚀刻第一多晶硅层来暴露图案化的衬垫氧化物层的至少一部分; 在所述第一多晶硅层上沉积金属层以形成第一硅化物层; 在具有第一硅化物层的衬底上形成氧化物层,并暴露出基极 - 发射极结和集电极区域; 通过在暴露的基极 - 发射极结和集电极区域上沉积第二多晶硅层来形成发射极和集电极; 以及在所述发射极和集电极上沉积金属层以形成第二硅化物层,以及形成基极端子,发射极端子和集电极端子。 在该方法中,可以降低基极寄生电阻,在硅化物层的形成期间可以防止由Ge引起的聚集引起的电短路,并且可以使用衬垫氧化物层从外部工艺来保护基极 - 发射极结,从而 提高工艺稳定性和可靠性。