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31. 发明授权

US08084863B2 Circuitized substrate with continuous thermoplastic support film dielectric layers 失效
标题翻译：具有连续热塑性支撑膜电介质层的电路基板
公开(公告)号：US08084863B2
公开(公告)日：2011-12-27
申请号：US12081051
申请日：2008-04-10
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
IPC分类号： H01L23/50
CPC分类号： H01L23/145 , H01L23/3733 , H01L23/3735 , H01L23/4922 , H01L23/49822 , H01L23/49827 , H01L23/564 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/12044 , H01L2924/15311 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0209 , H05K2201/0278 , H05K2201/068 , Y10T29/4913 , H01L2224/0401
摘要： A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
摘要翻译：一种电路化基板，包括具有浸渍有无卤低吸湿树脂的对芳族聚酰胺纸，并且不包括作为其一部分的连续或半连续玻璃纤维纤维的介电层和位于介电层上的第一电路层。还提供了制造该基板的方法。

32. 发明授权

US07646098B2 Multilayered circuitized substrate with p-aramid dielectric layers and method of making same 失效
标题翻译：具有对芳族聚酰胺介电层的多层电路基板及其制造方法
公开(公告)号：US07646098B2
公开(公告)日：2010-01-12
申请号：US12081042
申请日：2008-04-10
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
IPC分类号： H01L23/485
CPC分类号： H01L23/145 , H01L23/3733 , H01L23/3735 , H01L23/4922 , H01L23/49822 , H01L23/49827 , H01L23/564 , H01L2924/0002 , H01L2924/12044 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0209 , H05K2201/0278 , H05K2201/068 , Y10T29/4913 , Y10T156/10 , H01L2924/00
摘要： A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
摘要翻译：一种多层电路化基板，包括多个介电层，每个电介质层由浸渍有不含卤素的低吸湿性树脂的对芳族聚酰胺纸构成，所述不含卤素的低吸湿性树脂包括无机填料，但不包括连续或半连续的玻璃纤维作为其一部分，电路层位于第一介电层上。还提供了制造该基板的方法。

33. 发明申请

US20090301770A1 EMBEDDED THIN FILMS 有权
标题翻译：嵌入式薄膜
公开(公告)号：US20090301770A1
公开(公告)日：2009-12-10
申请号：US12482202
申请日：2009-06-10
申请人： Junghyun Cho , Bahgat Sammakia , Mark D. Poliks , Roy Magnuson , Biplab Kumar Roy
发明人： Junghyun Cho , Bahgat Sammakia , Mark D. Poliks , Roy Magnuson , Biplab Kumar Roy
IPC分类号： H05K1/09 , C25D7/12
CPC分类号： H05K3/0011 , C25D5/48 , C25D9/08 , C25D21/12 , H05K1/0306 , H05K1/09 , H05K1/162 , H05K1/167 , H05K3/184 , H05K2201/0175 , H05K2201/0355 , H05K2203/092 , H05K2203/135 , H05K2203/163
摘要： A method for forming a film on a conductive substrate, comprising immersing a substrate having a conductive portion in a solution comprising a metal ion ceramic precursor for the film and a peroxide; applying a voltage potential to the conductive portion with respect to a counter electrode in the solution, sufficient to protect the conductive portion from corrosion by the solution, and drive formation of a film on the substrate, controlling a pH of the solution while limiting a production of hydrogen by electrolysis of the solution proximate to the conductive portion; and maintaining the voltage potential for a sufficient duration to produce a film on the conductive portion. An electrode may be formed over the film to produce an electrical device. The film may be, for example, insulating, dielectric, resistive, semiconductive, magnetic, or ferromagnetic.
摘要翻译：一种在导电性基板上形成膜的方法，其特征在于，将具有导电性部分的基板浸渍在包含所述膜的金属离子陶瓷前体和过氧化物的溶液中; 对导电部分相对于溶液中的对电极施加电压电位，足以保护导电部分免受溶液的腐蚀，并且驱动在衬底上形成膜，控制溶液的pH，同时限制生产的氢气通过电解接近导电部分的溶液; 并且保持电压电位足够的持续时间以在导电部分上产生膜。可以在膜上形成电极以产生电气装置。该膜可以是例如绝缘，电介质，电阻，半导体，磁性或铁磁性的。

34. 发明授权

US07541058B2 Method of making circuitized substrate with internal optical pathway 有权
公开(公告)号：US07541058B2
公开(公告)日：2009-06-02
申请号：US11907006
申请日：2007-10-09
申请人： Benson Chan , How T. Lin , Roy H. Magnuson , Voya R. Markovich , Mark D. Poliks
发明人： Benson Chan , How T. Lin , Roy H. Magnuson , Voya R. Markovich , Mark D. Poliks
IPC分类号： G02B6/02 , H01L21/00 , G03G15/00 , G02B6/12
CPC分类号： G02B6/1221 , G02B6/132 , G02B6/136 , G02B6/4214 , G02B6/4246 , H05K1/0274
摘要： A circuitized substrate (e.g., PCB) including an internal optical pathway as part thereof such that the substrate is capable of transmitting and/or receiving both electrical and optical signals. The substrate includes an angular reflector on one of the cladding layers such that optical signals passing through the optical core will impinge on the angled reflecting surfaces of the angular reflector and be reflected up through an opening (including one with optically transparent material therein), e.g., to a second circuitized substrate also having at least one internal optical pathway as part thereof, to thus interconnect the two substrates optically. A method of making the substrate is also provided.

35. 发明授权

US06329603B1 Low CTE power and ground planes 有权
标题翻译：低CTE电源和接地层
公开(公告)号：US06329603B1
公开(公告)日：2001-12-11
申请号：US09288051
申请日：1999-04-07
申请人： Robert M. Japp , Mark D. Poliks
发明人： Robert M. Japp , Mark D. Poliks
IPC分类号： H05K103
CPC分类号： H05K3/4641 , H05K1/0366 , H05K2201/0141 , H05K2201/0158 , H05K2201/0278 , H05K2201/0281 , H05K2201/029 , H05K2201/0323 , H05K2201/068 , H05K2201/09309 , Y10S428/901 , Y10T29/49126 , Y10T29/49165
摘要： Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.
摘要翻译：公开了具有低热膨胀系数（CTE）并且用于电力和接地平面的导电材料。具有低CTE的纤维材料（例如碳，石墨，玻璃，石英，聚乙烯和液晶聚合物纤维）被金属化以提供具有低CTE的所得导电材料。这样的纤维可以以其单独状态进行金属化，然后形成织物，或者这些材料可以形成织物，然后金属化，或者可以使用两种金属化的组合。此外，石墨或碳片可以在一侧或两侧金属化，以提供具有低CTE和高导电性的材料。这些金属化的低CTE功率和接地层可以与其它平面/芯层压成复合材料，或者层压成芯，然后将其与其它平面/芯层叠合成复合材料。所得的复合材料可用于印刷电路板（PCB）或用作层压芯片载体的PCB。

36. 发明授权

US08288857B2 Anti-tamper microchip package based on thermal nanofluids or fluids 失效
标题翻译：基于热纳米流体或流体的防篡改微芯片封装
公开(公告)号：US08288857B2
公开(公告)日：2012-10-16
申请号：US12884421
申请日：2010-09-17
申请人： Rabindra N. Das , Voya R. Markovich , James J. McNamara, Jr. , Mark D. Poliks
发明人： Rabindra N. Das , Voya R. Markovich , James J. McNamara, Jr. , Mark D. Poliks
IPC分类号： H01L23/22 , H01L23/12
CPC分类号： H01L23/42 , H01L23/573 , H01L24/13 , H01L24/16 , H01L24/29 , H01L2224/13101 , H01L2224/16225 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29369 , H01L2224/29387 , H01L2224/29393 , H01L2224/73204 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.
摘要翻译：防篡改微芯片封装包含流体或纳米流体填充的胶囊，通道或储存器，其中单独或组合的流体可以在尝试逆向工程化时通过蚀刻，烧结或热破坏来破坏电路。当流体填充的空腔被切掉以便对微芯片进行详细检查时，释放流体。可以将纳米流体用于烧结过程，并且还可以增加用于管芯热管理的流体的热导率。通孔和微通孔可以并入设计中以通过改善流体/芯片接触来增加电路破坏功效。也可以使用热界面材料来促进芯片冷却。

37. 发明申请

US20120069531A1 CONDUCTING PASTE FOR DEVICE LEVEL INTERCONNECTS 有权
标题翻译：用于设备级互连的导电胶
公开(公告)号：US20120069531A1
公开(公告)日：2012-03-22
申请号：US12884657
申请日：2010-09-17
申请人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
发明人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
IPC分类号： H05K7/00 , H01B1/02 , H01B1/22 , H01R43/00
CPC分类号： H01B1/22 , H01L2224/81 , Y10T29/49117
摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
摘要翻译：导电糊和形成用于器件级互连的糊的方法。导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。通常，小于5微米的平均片尺寸适用于五微米互连。然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。最终混合物中基于LMP的糊剂的量优选为20-50重量％。纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

38. 发明授权

US07025607B1 Capacitor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate 失效
标题翻译：具有用于电路化基板的金属部件的电容器材料，利用其的电路化基板，制造所述电路化基板的方法以及利用所述电路化基板的信息处理系统
公开(公告)号：US07025607B1
公开(公告)日：2006-04-11
申请号：US11031074
申请日：2005-01-10
申请人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich , Mark D. Poliks
发明人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich , Mark D. Poliks
IPC分类号： H01R4/58
CPC分类号： H01G4/206 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/0102 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/162 , H05K3/0023 , H05K2201/0187 , H05K2201/0209 , H05K2201/0215 , H05K2201/0257 , H01L2224/0401
摘要： A material for use as part of an internal capacitor within a circuitized substrate includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ferroelectric ceramic component, the ferroelectric ceramic component nano-particles having a particle size substantially in the range of between about 0.01 microns and about 0.9 microns and a surface within the range of from about 2.0 to about 20 square meters per gram. A circuitized substrate adapted for using such a material and capacitor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.
摘要翻译：用作电路化基板内的内部电容器的一部分的材料包括聚合物树脂和一定数量的纳米粉末，其包括至少一种金属组分和至少一种铁电陶瓷组分的混合物，所述铁电陶瓷组分纳米颗粒具有基本上在约0.01微米至约0.9微米范围内的粒度和约2.0至约20平方米每克的表面。还提供了适于在其中使用这种材料和电容器的电路化基板和制造这种基板的方法。还提供电气组件（基板和至少一个电气部件）和信息处理系统（例如，个人计算机）。

39. 发明授权

US06944946B2 Porous power and ground planes for reduced PCB delamination and better reliability 失效
标题翻译：多功能电源和接地平面可降低PCB分层和更好的可靠性
公开(公告)号：US06944946B2
公开(公告)日：2005-09-20
申请号：US10430989
申请日：2003-05-06
申请人： Robert M. Japp , Mark D. Poliks
发明人： Robert M. Japp , Mark D. Poliks
IPC分类号： H05K1/02 , H05K3/38 , H05K3/42 , H05K3/46 , H01K3/10
CPC分类号： H05K3/38 , H05K3/429 , H05K3/4641 , H05K2201/0116 , H05K2201/0281 , H05K2201/029 , H05K2201/0769 , H05K2201/09309 , H05K2201/09681 , H05K2203/1131 , Y10S428/901 , Y10T29/49002 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1052 , Y10T428/24273 , Y10T428/24917
摘要： Power and ground planes that are used in Printed Circuit Boards (PCBs) and that comprise porous, conductive materials are disclosed. Using porous power and ground plane materials in PCBs allows liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.
摘要翻译：公开了在印刷电路板（PCB）中使用并且包含多孔导电材料的电源和接地层。在PCB中使用多孔电源和接地平面材料可以使液体（例如水和/或其他溶剂）通过电源和接地层，从而减少由阴极/阳极细丝引起的PCB（或PCBs用作层压芯片载体）的故障绝缘子的生长和分层。适用于PCB的多孔导电材料可以通过使用金属涂布的有机布（例如聚酯或液晶聚合物）或织物（例如由碳/石墨或玻璃纤维制成的那些）形成，使用金属丝网代替金属使用烧结金属，或者通过在金属板中形成孔阵列来制造多孔的金属片。织物和网可以编织或随机。如果在金属板中形成孔阵列，则可以形成这样的阵列，而不需要使用常规PCB组装方法执行的附加处理步骤。

40. 发明授权

US5194930A Dielectric composition and solder interconnection structure for its use 失效
标题翻译：电介质组成和焊料互连结构供其使用
公开(公告)号：US5194930A
公开(公告)日：1993-03-16
申请号：US760654
申请日：1991-09-16
申请人： Kostas Papathomas , Mark D. Poliks , David W. Wang , Frederick R. Christie
发明人： Kostas Papathomas , Mark D. Poliks , David W. Wang , Frederick R. Christie
IPC分类号： C09J163/00 , H01L21/56 , H01L23/29 , H01L23/31
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01014 , H01L2924/01019 , H01L2924/01087 , H01L2924/10253
摘要： Composition and solder interconnection structure for its use, wherein the gap created by solder connections between a carrier substrate and a semiconductor chip device mounted thereon is filled with the solvent free formulation obtained by curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof, polyol, and filler which is substantially free of alpha particle emissions.
摘要翻译：用于其使用的组合物和焊料互连结构，其中通过在载体衬底和安装在其上的半导体芯片器件之间的焊料连接产生的间隙填充有通过固化含有脂环族聚环氧化物和/或可固化氰酸酯的制剂而获得的无溶剂配方，或其预聚物，多元醇和基本上不含α粒子排放物的填料。

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