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31. 发明授权

US6087853A Controlled output impedance buffer using CMOS technology 失效
标题翻译：使用CMOS技术的受控输出阻抗缓冲器
公开(公告)号：US6087853A
公开(公告)日：2000-07-11
申请号：US100939
申请日：1998-06-22
申请人： Carol A. Huber , Bernard L. Morris , Bijit T. Patel
发明人： Carol A. Huber , Bernard L. Morris , Bijit T. Patel
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0005
摘要： CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.
摘要翻译： CMOS技术用于创建受控输出阻抗输出缓冲电路。输出缓冲器驱动器使用具有线性特性的阻抗元件的缓冲电路。控制电路使用已知的阻抗负载来控制缓冲电路的阻抗。控制电路监测流过已知阻抗负载的已知电流，以确定输出缓冲电路的输出阻抗是否需要调整以匹配传输线的阻抗。当控制电路产生控制信号以导通或关闭包含在输出驱动器内的各种缓冲电路（及其阻抗元件）时，发生调整。在这样做时，输出缓冲电路确保其输出阻抗将与输出电压的整个范围内的传输线的阻抗匹配，而不管制造过程，操作温度和电源电压引起的变化如何。

32. 发明授权

US5381062A Multi-voltage compatible bidirectional buffer 失效
标题翻译：多电压兼容双向缓冲器
公开(公告)号：US5381062A
公开(公告)日：1995-01-10
申请号：US144594
申请日：1993-10-28
申请人： Bernard L. Morris
发明人： Bernard L. Morris
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094 , H03K19/0948 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/09429 , H03K19/0948
摘要： An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor. The constant voltage source comprises a third field effect transistor having a drain and a gate connected to the third node, and a source coupled to a first power supply voltage, such that the gate voltage is substantially equal to the first power supply voltage minus a threshold voltage of the third transistor.
摘要翻译：公开了一种集成电路，其包括具有连接到第一节点的源极和连接到第二节点的栅极的第一场效应晶体管，以及用于保护第一晶体管免受施加到第一节点的电压的第二场效应晶体管，预定额定电压。第二晶体管包括连接到第二节点的漏极，连接到第一节点的源极和连接到第三节点的栅极。恒定电压源耦合到第三节点并且将栅极电压提供给第二晶体管的栅极，使得第二晶体管的漏极 - 源极路径不导通，而施加到第一节点的电压通常小于栅极电压加上第二晶体管的阈值电压。恒压源包括第三场效应晶体管，其具有连接到第三节点的漏极和栅极，以及耦合到第一电源电压的源极，使得栅极电压基本上等于第一电源电压减去阈值第三晶体管的电压。

33. 发明授权

US07590961B2 Integrated circuit with signal skew adjusting cell selected from cell library 失效
标题翻译：具有从单元库选择的信号偏移调整单元的集成电路
公开(公告)号：US07590961B2
公开(公告)日：2009-09-15
申请号：US11774022
申请日：2007-07-06
申请人： Martin J. Gasper, Jr. , Bernard L. Morris
发明人： Martin J. Gasper, Jr. , Bernard L. Morris
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H03K5/1565 , H03K19/00323
摘要： An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and the skew adjusting cell are selected from a cell library.
摘要翻译：集成电路包括具有至少一个数字逻辑单元和至少一个偏斜调整单元的数字电路。偏斜调整单元被配置为将集成电路的数字电路中的信号的偏斜调整到期望的量。从单元库中选择数字逻辑单元和偏斜调整单元。

34. 发明授权

US5933027A High-voltage-tolerant output buffers in low-voltage technology 失效
标题翻译：高电压技术中的高耐压输出缓冲器
公开(公告)号：US5933027A
公开(公告)日：1999-08-03
申请号：US879212
申请日：1997-06-19
申请人： Bernard L. Morris , Bijit T. Patel
发明人： Bernard L. Morris , Bijit T. Patel
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/00315
摘要： An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG. 1) based on an input voltage (e.g., A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.
摘要翻译：集成电路采用低压技术实现，并具有输出驱动器。输出驱动器具有适于基于输入电压（例如，A）在输出节点（例如，图1中的PAD）产生输出电压的电路。在输出驱动器内，晶体管被配置为限制跨另一晶体管的漏极 - 源极电压降，以使得集成电路在其输出节点容忍高达集成电路的工作电压的两倍的电压。本发明使得低电压集成电路能够与在相对高压技术中实现的其它电路接口，而不会产生不利影响，否则可能导致低压电路不受这种接口的影响。

35. 发明授权

US5894234A Differential comparator with fixed and controllable hysteresis 失效
标题翻译：具有固定和可控迟滞的差分比较器
公开(公告)号：US5894234A
公开(公告)日：1999-04-13
申请号：US846390
申请日：1997-04-30
申请人： Bernard L. Morris
发明人： Bernard L. Morris
IPC分类号： H03K3/3565 , H03K5/24 , H03F3/45 , H03F3/16
CPC分类号： H03K5/2481 , H03K3/3565
摘要： A differential comparator having a low-offset comparator and two processing paths, each of which receives one of the two primary inputs to the differential comparator and generates one of the two inputs to the low-offset comparator. The output of the low-offset comparator is the output of the differential comparator. Each processing path is capable of (1) generating an offset voltage and (2) turning on and off the generation of that offset voltage. In a preferred embodiment, each processing path has a passive resistor that generates the offset voltage and a pair of shunt transistors that selectively shorts out the passive resistor. The output of the low-offset comparator is connected (either directly or indirectly through an inverter) to the gates of the shunt transistors. The shunt transistors are therefore controlled by the output of the low-offset comparator. In each of two modes of operation, a different one of the passive resistors is "on" while the other passive resistor is "off." The result is a differential comparator that operates with hysteresis. The currents passing through the passive resistors to generate the offset voltages are mirrored from a current source that is controlled by a reference voltage. As such, the offset voltages can be controlled by adjusting the reference voltage. The differential comparator is capable therefore of operating with fixed and controllable hysteresis.
摘要翻译：具有低偏移比较器和两个处理路径的差分比较器，每个处理路径接收到差分比较器的两个主要输入中的一个，并产生两个输入中的一个到低偏移比较器。低偏移比较器的输出是差分比较器的输出。每个处理路径能够（1）产生偏移电压和（2）打开和关闭该偏移电压的产生。在优选实施例中，每个处理路径具有产生偏移电压的无源电阻器和选择性地使无源电阻器短路的一对分流晶体管。低偏移比较器的输出端（直接或间接通过反相器）连接到分流晶体管的栅极。因此，分流晶体管由低偏移比较器的输出控制。在两种工作模式中，不同的一种无源电阻为“开”，而另一种无源电阻为“关闭”。结果是一个差分比较器以滞后运行。通过无源电阻产生偏移电压的电流与由参考电压控制的电流源相反。因此，可以通过调整参考电压来控制偏移电压。差分比较器因此能够以固定和可控的滞后运行。

36. 发明授权

US5334885A Automatic control of buffer speed 失效
标题翻译：自动控制缓冲区速度
公开(公告)号：US5334885A
公开(公告)日：1994-08-02
申请号：US3751
申请日：1993-01-13
申请人： Bernard L. Morris
发明人： Bernard L. Morris
IPC分类号： H03M1/36 , H03K19/003 , H03K17/16 , H03K19/092
CPC分类号： H03K19/00384
摘要： The number of active switching elements in a buffer is automatically varied to compensate for variations in the manufacturing process, operating temperature, and power supply voltage. For this purpose, a reference voltage which is proportional to the speed of a switching transistor is applied to an analog-to-digital (A/D) converter. The A/D converter may be implemented with a simple resistor divider and comparators, all of which can be made on-chip. The resistor dividers are chosen such that at worst-case slow conditions all the comparators have high outputs. As the process/temperature/voltage changes, the reference voltage also increases. This successively turns off sections of the switching transistor, thereby slowing down the response of the buffer. Since the control leads are digital, they are not susceptible to noise as they are routed around a chip full of noisy signals. The digital control signals may be latched, and the control circuitry powered down to zero for powersensitive applications.
摘要翻译：缓冲器中的有源开关元件的数量自动变化以补偿制造工艺，工作温度和电源电压的变化。为此，将与开关晶体管的速度成比例的参考电压施加到模数（A / D）转换器。 A / D转换器可以用简单的电阻分压器和比较器来实现，所有这些都可以在片上制造。选择电阻分压器，使得在最差情况下，所有比较器都具有较高的输出。随着过程/温度/电压的变化，参考电压也会增加。这继续关闭开关晶体管的部分，从而减慢缓冲器的响应。由于控制引线是数字的，它们不会受到噪声的影响，因为它们绕着充满噪声信号的芯片布线。数字控制信号可能被锁存，并且控制电路对于功率敏感应用而降低到零。

37. 发明授权

US4645948A Field effect transistor current source 失效
标题翻译：场效应晶体管电流源
公开(公告)号：US4645948A
公开(公告)日：1987-02-24
申请号：US656343
申请日：1984-10-01
申请人： Bernard L. Morris , Jeffrey J. Nagy , Lawrence A. Walter
发明人： Bernard L. Morris , Jeffrey J. Nagy , Lawrence A. Walter
IPC分类号： G05F3/24 , G05F3/26 , H03K3/01 , H03K3/26 , H03K17/687
CPC分类号： G05F3/262 , Y10S323/907
摘要： A field effect transistor circuit generates a reference current that can obtain a desired temperature coefficient. The circuit is self-compensatory with respect to process variations, in that a "slow" process will produce a higher than normal current, while a "fast" process will give a lower one. This results in a tight spread of slew-rate, gain, gain-bandwidth, etc. in opamps, comparators, and other linear circuits. A simple adjustment in the circuit allows the temperature coefficient to be made positive or negative if so desired. An illustrative circuit is shown for CMOS technology, but can be applied to other field effect technologies.
摘要翻译：场效应晶体管电路产生可获得所需温度系数的参考电流。该电路对于过程变化是自补偿的，因为“慢”过程将产生高于正常电流，而“快速”过程将产生较低的电流。这导致了运算放大器，比较器和其他线性电路中压摆率，增益，增益带宽等的严格扩展。如果需要，电路中的简单调整允许温度系数为正或负。显示了CMOS技术的说明性电路，但可应用于其他场效应技术。

38. 发明授权

US5502328A Bipolar ESD protection for integrated circuits 失效
标题翻译：集成电路的双极ESD保护
公开(公告)号：US5502328A
公开(公告)日：1996-03-26
申请号：US228834
申请日：1994-04-18
申请人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
发明人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
IPC分类号： H01L27/02 , H01L29/00
CPC分类号： H01L27/0259
摘要： CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.
摘要翻译： CMOS集成电路缓冲器通常使用双二极管静电放电（ESD）保护技术。然而，在某些情况下，当在接合板上存在期望的信号电压时，该技术无意中导致二极管中的一个导通，从而限制期望的信号。例如，当未供电设备上的输出缓冲器连接到有源总线时，或者当3伏器件的输入缓冲器接收到5伏特信号时，就会发生这种情况。本发明通过使用连接在接合板和电源总线（例如VSS）之间的双极（例如，pnp）保护晶体管解决了该问题。晶体管的基极通过电阻器连接到接合板，电阻器由于包括分布电容的R-C时间常数而提供时间延迟。时间延迟允许高导通周期，在此期间ESD事件通过双极晶体管传导，从而保护输入或输出缓冲器。

39. 发明授权

US4912347A CMOS to ECL output buffer 失效
标题翻译： CMOS到ECL输出缓冲器
公开(公告)号：US4912347A
公开(公告)日：1990-03-27
申请号：US089284
申请日：1987-08-25
申请人： Bernard L. Morris
发明人： Bernard L. Morris
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0175 , H03K19/08 , H03K19/0944 , H03K19/0948
CPC分类号： H03K19/09448 , H03K19/0136 , H03K19/017518
摘要： A circuit is disclosed which converts CMOS logic input signals to ECL output signals. A pair of FETs, arranged as a conventional CMOS inverter, responds to the CMOS logic input signals and drives a bipolar transistor operating as a voltage follower. The emitter of the bipolar transistor serves as the output of the buffer providing the ECL output signals. A resistor having a predetermined resistance couples between a voltage source and the base of the bipolar transistor. First one of the pair of FETs couples a constant current source to the resistor and the base of the bipolar transistor when the buffer is supplying an ECL logical "zero" logic signal. The current from the current source passing through the resistor establishes the ECL logical "zero" output voltage. Second one of the pair of FETs shunts the resistor when the buffer is supplying an ECL logical "one" output, allowing faster transitioning of the output of the buffer from an ECL logical "zero" to a logical "one". Further, the current from the current source compensates for variations in the resistance of the resistor to assure a substantially constant difference between the ECL logical "one" and the ECL logical "zero" output voltages with variations in the resistance of the resistor from the manufacture thereof.

40. 发明授权

US06184700B2 Fail safe buffer capable of operating with a mixed voltage core 有权
标题翻译：能够使用混合电压核心工作的故障安全缓冲器
公开(公告)号：US06184700B2
公开(公告)日：2001-02-06
申请号：US09318158
申请日：1999-05-25
申请人： Bernard L. Morris
发明人： Bernard L. Morris
IPC分类号： H03K19007
CPC分类号： H03K19/007 , H03K19/00315
摘要： A voltage blocking circuit is disclosed, useable in a buffer portion of an integrated circuit, for a buffer portion of an IC chip that operates from a power supply different from the power supply that powers the core logic; however, the buffer remains in a high impendence state, regardless of whether or not power is supplied to the core logic.
摘要翻译：公开了一种可用于集成电路的缓冲部分的电压阻断电路，用于IC芯片的缓冲部分，该IC芯片的缓冲部分从不同于对核心逻辑电源供电的电源供电; 然而，无论电源是否被提供给核心逻辑，缓冲器保持高阻止状态。

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