专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07935620B2 Method for forming semiconductor devices with low leakage Schottky contacts 有权
标题翻译：用于形成具有低泄漏肖特基接触的半导体器件的方法
公开(公告)号：US07935620B2
公开(公告)日：2011-05-03
申请号：US11950820
申请日：2007-12-05
申请人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
发明人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
IPC分类号： H01L21/28
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
摘要翻译：半导体器件描述了方法和装置。一种方法包括提供部分完成的半导体器件，其包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分，并且不移除第一掩模，在半导体的暴露部分上形成第一材料的肖特基接触，然后去除第一掩模，并且使用另外的掩模，形成电耦合到肖特基接触和上覆部分的第二材料的阶梯栅导体的钝化层与肖特基接触相邻。通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

32. 发明授权

US07821103B2 Counter-doped varactor structure and method 有权
标题翻译：反掺杂变容二极管结构和方法
公开(公告)号：US07821103B2
公开(公告)日：2010-10-26
申请号：US12207127
申请日：2008-09-09
申请人： Chun-Li Liu , Olin K. Hartin , Jay P. John , Vishal P. Trivedi , James A. Kirchgessner
发明人： Chun-Li Liu , Olin K. Hartin , Jay P. John , Vishal P. Trivedi , James A. Kirchgessner
IPC分类号： H01L29/93
CPC分类号： H01L29/66174 , H01L29/93
摘要： An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.
摘要翻译：通过提供一种具有第一表面（43）的衬底（41），其中在第一表面（43）附近形成有P +区域（53,46），第一N区域（54），45），位于所述P +区（53,46）下方的N阱区（56,44）和位于所述第一N区（54,45）之下的第一P反掺杂区（55）区域（54,45）和N阱区域（56,44），从而形成用于变容二极管的P + NPN结构。在一些实施例中，第二P型反掺杂区域（59）设置在N阱区域（56,44）内，以便减小N阱区域（56,44）内的N掺杂浓度，但是不产生其中一个PN结。净掺杂分布（52）提供具有比可变电抗器（20）更大的调谐比率的变容二极管（40），而不具有这样的反掺杂区域。通过交换N和P区域，获得N + PNP变容二极管。

33. 发明授权

US07241647B2 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US07241647B2
公开(公告)日：2007-07-10
申请号：US10919952
申请日：2004-08-17
申请人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/00
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

34. 发明授权

US07221006B2 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US07221006B2
公开(公告)日：2007-05-22
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

35. 发明申请

US20070096226A1 MOSFET dielectric including a diffusion barrier 审中-公开
标题翻译： MOSFET电介质包括扩散阻挡层
公开(公告)号：US20070096226A1
公开(公告)日：2007-05-03
申请号：US11264069
申请日：2005-10-31
申请人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , James Schaeffer , Matthew Stoker
发明人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , James Schaeffer , Matthew Stoker
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28211 , H01L29/517 , H01L29/665 , H01L29/66575
摘要： A semiconductor device includes a substrate, a multilayered assembly of high k dielectric materials formed on the substrate, and a first conducting material formed on the upper layer of the assembly of high k dielectric materials. The multilayered high k dielectric assembly includes a lower layer, an upper layer, and a diffusion barrier layer formed between the lower and upper dielectric layers. The diffusion barrier layer has a greater affinity for oxygen than the upper and lower layers. The first conducting layer includes a conducting compound of at least a metal element and oxygen.
摘要翻译：半导体器件包括衬底，形成在衬底上的高k电介质材料的多层组件和形成在高k电介质材料的组件的上层上的第一导电材料。多层高k电介质组件包括下层，上层和形成在下介电层和上电介质层之间的扩散阻挡层。扩散阻挡层与上层和下层具有比氧更大的亲和性。第一导电层包括至少金属元素和氧的导电化合物。

36. 发明授权

US06518070B1 Process of forming a semiconductor device and a semiconductor device 失效
标题翻译：形成半导体器件和半导体器件的工艺
公开(公告)号：US06518070B1
公开(公告)日：2003-02-11
申请号：US09571586
申请日：2000-05-17
申请人： Prasad V. Alluri , Mark Victor Raymond , Sucharita Madhukar , Roland R. Stumpf , Chun-Li Liu , Clarence J. Tracy
发明人： Prasad V. Alluri , Mark Victor Raymond , Sucharita Madhukar , Roland R. Stumpf , Chun-Li Liu , Clarence J. Tracy
IPC分类号： H01L2170
CPC分类号： H01L21/3212 , H01L27/1057 , H01L27/108 , H01L27/10844 , H01L27/10852 , H01L27/10882 , H01L28/55 , H01L28/60 , H01L28/65
摘要： A process for forming a capacitor with a high-k dielectric or ferroelectric layer within a semiconductor device is used to reduce the likelihood of oxidation or materials interactions between that layer and an underlying layer. A first electrode layer includes atoms that form along grain boundaries within the first electrode layer to reduce the oxidation of a conductive plug or undesired materials interactions.
摘要翻译：用于在半导体器件内形成具有高k电介质层或铁电体层的电容器的工艺被用于降低该层与下层之间的氧化或材料相互作用的可能性。第一电极层包括沿第一电极层内的晶界形成的原子，以减少导电塞的氧化或不期望的材料相互作用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式