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31. 发明授权

US08380777B2 Normal-basis to canonical-basis transformation for binary galois-fields GF(2m) 有权
标题翻译：二进制Galois-field的典型基变换法（2m）
公开(公告)号：US08380777B2
公开(公告)日：2013-02-19
申请号：US11772176
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.
摘要翻译：对于通用多项式和以所有形式的所有形式的特殊不可约多项式提供了从正常形式到规范形式的基础转换，称为全要素多项式（AOP）。通过在飞行中创建矩阵，或者通过提供以最小的硬件扩展来计算结果的替代方法来最小化大矩阵的生成和存储。

32. 发明授权

US08316191B2 Memory controllers for processor having multiple programmable units 有权
标题翻译：具有多个可编程单元的处理器的存储器控制器
公开(公告)号：US08316191B2
公开(公告)日：2012-11-20
申请号：US12207476
申请日：2008-09-09
申请人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
发明人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

33. 发明授权

US07986779B2 Efficient elliptic-curve cryptography based on primality of the order of the ECC-group 有权
标题翻译：基于ECC组的顺序的有效椭圆曲线加密
公开(公告)号：US07986779B2
公开(公告)日：2011-07-26
申请号：US11772170
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , G06F7/72
CPC分类号： G06F7/725 , G06F5/01
摘要： Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.
摘要翻译：通过最小化移位操作的数量来减少执行用于ECC的标量点乘法的时间。通过基于ECC组的顺序的基本原理执行中间计算的点的选择性比较，通过应用模量缩放来最小化这些操作。

34. 发明申请

US20100153829A1 RESIDUE GENERATION 失效
标题翻译：残留生成
公开(公告)号：US20100153829A1
公开(公告)日：2010-06-17
申请号：US12336029
申请日：2008-12-16
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
IPC分类号： H03M13/09 , G06F7/72 , G06F11/10
CPC分类号： G06F7/724 , H03M13/091
摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.
摘要翻译：在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少是乘法的结果。所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

35. 发明授权

US07610451B2 Data transfer mechanism using unidirectional pull bus and push bus 有权
标题翻译：数据传输机制采用单向拉总线和推送总线
公开(公告)号：US07610451B2
公开(公告)日：2009-10-27
申请号：US10057738
申请日：2002-01-25
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F9/3824 , G06F9/3851
摘要： A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.
摘要翻译：一种用于在编程代理和存储器资源之间传送数据的方法。该方法包括在处理代理和存储器资源之间传送数据，指定存储器资源，用于经由具有仲裁使用推送总线的多个源的推送总线将数据推送到处理代理，以及指定用于接收的存储器资源来自处理代理的数据经由具有仲裁使用拉总线的多个目的地的拉总线。

36. 发明授权

US07539718B2 Method and apparatus for performing Montgomery multiplications 失效
标题翻译：执行蒙哥马利乘法的方法和装置
公开(公告)号：US07539718B2
公开(公告)日：2009-05-26
申请号：US10944354
申请日：2004-09-16
申请人： Kamal J. Koshy , Gilbert Wolrich , Jaroslaw J. Sydir , Wajdi K. Feghali
发明人： Kamal J. Koshy , Gilbert Wolrich , Jaroslaw J. Sydir , Wajdi K. Feghali
IPC分类号： G06F7/38
CPC分类号： G06F7/728 , G06F2207/3884
摘要： An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.
摘要翻译：提供了执行蒙哥马利乘法的安排。蒙哥马利乘法包括多个基本操作的迭代（例如，进位保存添加），并且由蒙哥马利乘法引擎（MME）执行。每个迭代中的基本操作可以由多个蒙哥马利乘法处理元件（MMPE）执行。 MME可以被布置成管理执行多个基本操作的迭代的过程以及完成水平和垂直的蒙哥马利乘法所需的其他操作。还可以将MME布置成交织执行两个蒙哥马利乘法的处理。

37. 发明授权

US07487505B2 Multithreaded microprocessor with register allocation based on number of active threads 有权
标题翻译：基于活动线程数的多线程微处理器，具有寄存器分配
公开(公告)号：US07487505B2
公开(公告)日：2009-02-03
申请号：US10212945
申请日：2002-08-05
申请人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein
发明人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein
IPC分类号： G06F9/46 , G06F15/00 , G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44 , G06F12/00 , G06F12/02
CPC分类号： G06F9/3885 , G06F9/30098 , G06F9/30123 , G06F9/3851
摘要： A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.
摘要翻译：多线程处理器中基于配置信息分配资源的机制，该配置信息指示正在使用多少线程。

38. 发明授权

US07424579B2 Memory controller for processor having multiple multithreaded programmable units 有权
标题翻译：具有多个多线程可编程单元的处理器的存储器控制器
公开(公告)号：US07424579B2
公开(公告)日：2008-09-09
申请号：US11232566
申请日：2005-09-21
申请人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
发明人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。所述处理器还包括存储器控制系统，所述存储器控制系统具有第一存储器控制器，所述第一存储器控制器基于所述存储器引用是针对偶数存储体还是存储器的奇数存储器排序存储器引用;以及第二存储器控制器，内存引用是读取引用或写入引用。

39. 发明授权

US07418571B2 Memory interleaving 有权
标题翻译：内存交错
公开(公告)号：US07418571B2
公开(公告)日：2008-08-26
申请号：US11112047
申请日：2005-04-22
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Matthew J. Adiletta
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Matthew J. Adiletta
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.
摘要翻译：存储器交错包括在计算系统中提供两个通道的非功率，并且在通道之间交织存储器访问。

40. 发明授权

US07418540B2 Memory controller with command queue look-ahead 有权
标题翻译：带有命令队列的内存控制器
公开(公告)号：US07418540B2
公开(公告)日：2008-08-26
申请号：US10834597
申请日：2004-04-28
申请人： Natarajan Rohit , Debra Bernstein , Gilbert Wolrich , Chang-Ming Lin
发明人： Natarajan Rohit , Debra Bernstein , Gilbert Wolrich , Chang-Ming Lin
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F13/161
摘要： In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in part, on the memory access operations identified by the commands and the memory access operation of a previously selected memory access commands.
摘要翻译：通常，在一个方面，本公开描述了从与随机存取存储器（RAM）的相应的存储体组相关联的多个存储器访问命令队列之一访问多个存储器访问命令，并且至少部分地基于所述命令来选择一个命令关于由命令识别的存储器访问操作和先前选择的存储器访问命令的存储器访问操作。

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