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31. 发明申请

US20090089568A1 Securely Launching Encrypted Operating Systems 有权
标题翻译：安全启动加密操作系统
公开(公告)号：US20090089568A1
公开(公告)日：2009-04-02
申请号：US11864418
申请日：2007-09-28
申请人： Kevin M. Litwack , Kenneth D. Ray , David R. Wooten , Nathan T. Lewis
发明人： Kevin M. Litwack , Kenneth D. Ray , David R. Wooten , Nathan T. Lewis
IPC分类号： G06F15/177
CPC分类号： G06F15/16
摘要： Tools and techniques for securely launching encrypted operating systems are described herein. The tools may provide computing systems that include operating systems (OSs) that define boot paths for the systems. This boot path may include first and second OS loader components. The first loader may include instructions for retrieving a list of disk sectors from a first store, and for retrieving these specified sectors from an encrypted second store. The first loader may also store the sectors in a third store that is accessible to both the first and the second loader components, and may invoke the second loader to try launching the OS using these sectors. In turn, the second loader may include instructions for retrieving these sectors from the third store, and for unsealing a key for decrypting these sectors. The second loader may then decrypt these sectors, and attempt to launch the OS from these sectors.
摘要翻译：本文描述了用于安全启动加密操作系统的工具和技术。这些工具可以提供包括为系统定义引导路径的操作系统（OS）的计算系统。该引导路径可以包括第一和第二OS加载器组件。第一加载器可以包括用于从第一存储检索磁盘扇区列表的指令，并且用于从加密的第二存储中检索这些指定的扇区。第一加载器还可以将扇区存储在第一和第二加载器组件可访问的第三个存储区中，并且可以调用第二加载器来尝试使用这些扇区启动操作系统。反过来，第二装载器可以包括用于从第三商店检索这些扇区的指令，以及用于解密用于对这些扇区进行解密的密钥。然后，第二加载器可以解密这些扇区，并尝试从这些扇区启动OS。

32. 发明授权

US6073186A Low speed serial bus protocol and circuitry 失效
标题翻译：低速串行总线协议和电路
公开(公告)号：US6073186A
公开(公告)日：2000-06-06
申请号：US796978
申请日：1997-02-07
申请人： David E. Murray , David R. Wooten
发明人： David E. Murray , David R. Wooten
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4295
摘要： A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.
摘要翻译：一种用于低速串行总线功能的串行总线通信方法和电路。通过双线通信通道，单向时钟线和双向数据线用于传输数据。协议定义权限，确认，终止和重试之间的握手点。提供电路，用于在与低速功能配合时减少串行总线的延迟。公开了用于将高电压信号转换成较低电压信号的电阻连接方案。

33. 发明授权

US5802318A Universal serial bus keyboard system 失效
标题翻译：通用串行总线键盘系统
公开(公告)号：US5802318A
公开(公告)日：1998-09-01
申请号：US506884
申请日：1995-07-25
申请人： David E. Murray , David R. Wooten , Randall L. Hess , Christopher C. Wanner , Jeff W. Wolford
发明人： David E. Murray , David R. Wooten , Randall L. Hess , Christopher C. Wanner , Jeff W. Wolford
IPC分类号： G06F3/023 , G06F3/038 , G06F9/445 , G06F13/10 , G06F13/12 , G06F3/00 , G06F9/46
CPC分类号： G06F3/038 , G06F13/105 , G06F13/126 , G06F3/023 , G06F9/4411
摘要： A keyboard system according to the present invention includes a serial bus host controller coupled to a serial bus keyboard. The keyboard includes both keyboard scan logic and scan code conversion logic for passing to the host controller over the serial bus. The host controller includes circuitry for processing the data between the serial bus and a host bus. The host controller further includes 8042 emulation logic for providing a hardware compatible interface to the keyboard controller. The 8042 emulation logic also includes circuitry for communicating over the serial bus during times when the serial bus has not yet been initialized.
摘要翻译：根据本发明的键盘系统包括耦合到串行总线键盘的串行总线主机控制器。键盘包括键盘扫描逻辑和扫描码转换逻辑，用于通过串行总线传送到主机控制器。主机控制器包括用于处理串行总线和主机总线之间的数据的电路。主机控制器还包括用于向键盘控制器提供硬件兼容接口的8042仿真逻辑。 8042仿真逻辑还包括在串行总线尚未初始化的时间内通过串行总线通信的电路。

34. 发明授权

US5644755A Processor with virtual system mode 失效
标题翻译：具有虚拟系统模式的处理器
公开(公告)号：US5644755A
公开(公告)日：1997-07-01
申请号：US394680
申请日：1995-02-24
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F9/455 , G06F12/02 , G06F13/10 , G06F12/10
CPC分类号： G06F9/45533 , G06F12/0292 , G06F13/105 , G06F2212/206
摘要： A processor having the prior three user addressing modes and a new virtual system mode (VSM). The user modes include real mode, protected mode and virtual 8086 mode. In VSM, the processor can utilize the VSM addressing mechanism and the mode of operation prior to entering VSM. Transitions from the user modes to virtual system mode can be made by indirect calls through a call gate or through vectored entries. While in VSM the processor can utilize VSM memory and I/O space modes, but can also directly utilize the I/O space and memory of the user mode present prior to entry into VSM by using a segment override. The upper 16MB of the virtual system mode memory space (0.times.ff000000 through 0.times.ffffffff) is designated as non-mapped virtual system mode memory. Virtual system mode logical addresses below 0.times.ff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode). Upon exiting VSM, any processor registers that were saved are restored so the user mode operation can continue as if the emulation operation were performed by the normal interrupt service routine.
摘要翻译：具有先前三种用户寻址模式的处理器和新的虚拟系统模式（VSM）。用户模式包括实模式，保护模式和虚拟8086模式。在VSM中，处理器可以在进入VSM之前利用VSM寻址机制和运行模式。从用户模式到虚拟系统模式的转换可以通过通过呼叫门或通过向量输入的间接呼叫进行。在VSM中，处理器可以利用VSM存储器和I / O空间模式，但也可以通过使用段重写来直接利用在进入VSM之前存在的用户模式的I / O空间和存储器。虚拟系统模式存储空间（0xff000000至0xffffffff）的高16MB被指定为非映射虚拟系统模式存储器。如果分页启用（保护模式），虚拟系统模式逻辑地址低于0xff000000将被当前页表转换为物理地址。退出VSM后，任何已保存的处理器寄存器将被恢复，以便用户模式操作可以继续，仿佛仿真操作由正常中断服务程序执行。

35. 发明授权

US5523755A N-key rollover keyboard without diodes 失效
标题翻译：没有二极管的N键翻转键盘
公开(公告)号：US5523755A
公开(公告)日：1996-06-04
申请号：US149971
申请日：1993-11-10
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： H03M11/00 , H03K17/94
CPC分类号： H03M11/003
摘要： A n-key rollover keyboard having an application specific integrated circuit (ASIC) with a large number of pins, each pin directly connected to a key contact, with the other side of the key contact connected to ground. The direct wire arrangement allows use of a single sided circuit board. The keyboard has a reduced cost over prior n-key rollover designs by allowing removal of the series diodes and double sided circuit board.
摘要翻译：具有多个引脚的专用集成电路（ASIC）的n键翻转键盘，每个引脚直接连接到键触点，键触点的另一侧连接到地。直接导线布置允许使用单面电路板。通过允许去除串联二极管和双面电路板，键盘比以前的n键翻转设计具有更低的成本。

36. 发明授权

US4351034A Folded bit line-shared sense amplifiers 失效
标题翻译：折叠位线共享读出放大器
公开(公告)号：US4351034A
公开(公告)日：1982-09-21
申请号：US195728
申请日：1980-10-10
申请人： Sargent S. Eaton, Jr. , David R. Wooten
发明人： Sargent S. Eaton, Jr. , David R. Wooten
IPC分类号： G11C11/419 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4097 , G11C11/409 , G11C11/4091
摘要： A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second isolation transistors. The same shared sense amplifier is also positioned between and coupled to third and fourth bit lines via third and fourth isolation transistors. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a selected bit line and a dummy cell capacitor is coupled to the bit line adjacent the selected bit line. A decoding circuit selectively activates the shared sense amplifier to sense a difference in voltage between the selected bit line and its adjacent bit line so as to determine the logic state associated with the accessed memory cell. Then, the sense amplifier latches into this logic state for reading by the input/output buss lines. After the logic state is read, the selecting circuit enables the memory cell capacitor to be refreshed for further sensing by the sense amplifier.
摘要翻译：描述折叠的位线共享读出放大器装置，用于感测动态MOS随机存取存储器中访问的存储器单元的逻辑状态。在优选实施例中，共享读出放大器位于第一和第二隔离晶体管之间并且耦合到第一和第二位线。相同的共享读出放大器也位于第三和第四隔离晶体管之间并且耦合到第三和第四位线。当要访问的存储器单元的状态时，其存储单元电容器被耦合到所选位线，并且虚设单元电容器耦合到与选定位线相邻的位线。解码电路选择性地激活共享读出放大器以感测所选位线与其相邻位线之间的电压差，以便确定与所访问的存储器单元相关联的逻辑状态。然后，读出放大器锁存到该逻辑状态，以便通过输入/输出总线进行读取。在读取逻辑状态之后，选择电路使存储单元电容器被刷新以便由读出放大器进一步感测。

37. 发明授权

US07917723B2 Address translation table synchronization 有权
标题翻译：地址转换表同步
公开(公告)号：US07917723B2
公开(公告)日：2011-03-29
申请号：US11291726
申请日：2005-12-01
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used to update an entry within the address translation table corresponding to the virtual address according to the indicated physical memory location.
摘要翻译：一种用于更新地址转换表的系统，方法和计算机可读介质。在该方法中，从处理器接收指示对应于虚拟地址的物理存储器位置的消息。 I / O存储器管理单元（IOMMU）用于根据指示的物理存储器位置更新对应于虚拟地址的地址转换表中的条目。

38. 发明授权

US07499057B2 Address translation in an integrated graphics environment 有权
标题翻译：在集成图形环境中进行地址转换
公开(公告)号：US07499057B2
公开(公告)日：2009-03-03
申请号：US11222551
申请日：2005-09-09
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F12/10 , G06F9/26
CPC分类号： G06F12/1009
摘要： A method of translating graphics virtual addresses to physical addresses in an integrated graphics processor environment includes receiving a request for a graphics operation from an application. The application may be an application executing in a partition of a virtual machine. The requested graphics operation involves at least one instruction and at least one graphics virtual address. The instructions are accessed and execution begins by instruction execution within a graphics processor. The graphics processor relies upon an I/O memory management unit to perform a virtual address to physical address translation as the graphics processor performs the graphics operation. The I/O memory management unit may utilize direct memory access to accomplish the graphics operation.
摘要翻译：将图形虚拟地址转换为集成图形处理器环境中的物理地址的方法包括从应用程序接收对图形操作的请求。应用程序可以是在虚拟机的分区中执行的应用程序。所请求的图形操作涉及至少一个指令和至少一个图形虚拟地址。指令被访问，并且执行由图形处理器内的指令执行开始。当图形处理器执行图形操作时，图形处理器依靠I / O存储器管理单元执行物理地址转换的虚拟地址。 I / O存储器管理单元可以利用直接存储器访问来完成图形操作。

39. 发明授权

US06542946B1 Dual mode differential transceiver for a universal serial bus 有权
标题翻译：用于通用串行总线的双模式差分收发器
公开(公告)号：US06542946B1
公开(公告)日：2003-04-01
申请号：US09493322
申请日：2000-01-28
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F1342
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： A computer system has a USB bus to which one or more USB-compatible devices can connect. One or more of the USB devices has an electrical interface that includes two transmitters and, if desired, a receiver for bidirectional data transmission. The transmitters preferably are dual output, differential transmitters. The transmitters include a slower transmitter and a faster transmitter. The faster transmitter can transmit data at a rate that is faster than the slower transmitter. The electrical interface also includes an electrical termination device that is disposed between the output terminals of the two transmitters. The termination device preferably comprises a pair of multi-purpose termination resistors that can provide serial termination or parallel termination depending whether the fast or slow transmitter is used. When transmitting using the slower transmitter, the receiving USB device disables all of its transmitters and the transmitting USB device disables the output of the faster transmitter by deasserting an output enable (OE) signal to the faster transmitter. The termination device provides serial termination and the data from the slower transmitter passes through the termination device. When transmitting using the faster transmitter, both receiving and transmitting USB devices assert single ended zero (SE0) signals to their slower transmitters which forces both of the slower transmitters' output signals to a low impedance state. In this latter transmission mode, the termination device provides parallel termination, effectively functioning as a “pull-down” terminator. With parallel termination, echoes effectively are reduced or eliminated and faster data rates are thereby attainable than are generally possible with serially-terminated transmission lines.
摘要翻译：计算机系统具有一个USB总线，一个或多个USB兼容设备可以连接到该总线。一个或多个USB设备具有电接口，其包括两个发射器，并且如果需要，包括用于双向数据传输的接收器。发射机最好是双输出差分发射机。发射机包括较慢的发射机和更快的发射机。更快的发射机可以以比较慢的发射机更快的速率传输数据。电接口还包括设置在两个发射器的输出端之间的电终端装置。终端设备优选地包括一对多用途终端电阻器，其可以根据是使用快速还是慢速发射机来提供串行终止或并行终端。当使用较慢的发射机进行传输时，接收的USB设备会禁用其所有发射机，并且发射的USB设备通过将更快的发射机的输出使能（OE）信号置低，来禁用较快发射机的输出。终端设备提供串行终端，来自较慢发射机的数据通过终端设备。当使用更快的发射机进行发射时，接收和发射USB设备都将其单端零（SE0）信号置于其较慢的发射机，这些发射机将较慢的发射机的输出信号强制为低阻抗状态。在后一种传输模式中，终端设备提供并行终端，有效地用作“下拉”终端器。通过并行终止，减少或消除回波，从而可以实现比串行端接的传输线通常可以实现更快的数据速率。

40. 发明授权

US5832299A System for emulating input/output devices utilizing processor with virtual system mode by allowing mode interpreters to operate concurrently on different segment registers 失效
标题翻译：利用具有虚拟系统模式的处理器来模拟输入/输出设备的系统，允许模式解释器在不同的段寄存器上同时运行
公开(公告)号：US5832299A
公开(公告)日：1998-11-03
申请号：US882823
申请日：1997-06-26
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F9/455 , G06F12/02 , G06F13/10 , G06F12/10
CPC分类号： G06F9/45533 , G06F12/0292 , G06F13/105 , G06F2212/206
摘要： A processor having the prior three user addressing modes and a new virtual system mode (VSM). The user modes include real mode, protected mode and virtual 8086 mode. In VSM, the processor can utilize the VSM addressing mechanism and the mode of operation prior to entering VSM. Transitions from the user modes to virtual system mode can be made by indirect calls through a call gate or through vectored entries. While in VSM the processor can utilize VSM memory and I/O space modes, but can also directly utilize the I/O space and memory of the user mode present prior to entry into VSM by using a segment override. The upper 16 MB of the virtual system mode memory space (0xff000000 through 0xffffffff) is designated as non-mapped virtual system mode memory. Virtual system mode logical addresses below 0xff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode). Upon exiting VSM, any processor registers that were saved are restored so the user mode operation can continue as if the emulation operation were performed by the normal interrupt service routine.
摘要翻译：具有先前三种用户寻址模式的处理器和新的虚拟系统模式（VSM）。用户模式包括实模式，保护模式和虚拟8086模式。在VSM中，处理器可以在进入VSM之前利用VSM寻址机制和操作模式。从用户模式到虚拟系统模式的转换可以通过通过呼叫门或通过向量输入的间接呼叫进行。在VSM中，处理器可以利用VSM存储器和I / O空间模式，但也可以通过使用段重写来直接利用在进入VSM之前存在的用户模式的I / O空间和存储器。虚拟系统模式存储空间（0xff000000至0xffffffff）的高16 MB被指定为非映射虚拟系统模式存储器。如果分页启用（保护模式），虚拟系统模式逻辑地址低于0xff000000将被当前页表转换为物理地址。退出VSM后，任何已保存的处理器寄存器将被恢复，以便用户模式操作可以继续，仿佛仿真操作由正常中断服务程序执行。

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