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31. 发明申请

US20080046658A1 Data Processing System and Method for Predictively Selecting a Scope of a Prefetch Operation 失效
标题翻译：用于预测选择预取操作范围的数据处理系统和方法
公开(公告)号：US20080046658A1
公开(公告)日：2008-02-21
申请号：US11465587
申请日：2006-08-18
申请人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F12/0862
摘要： A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, and a cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents of the data array, and a cache controller including a prefetch predictor. The prefetch predictor determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address. The cache controller issues the first prefetch operation on the interconnect fabric with the predicted scope.
摘要翻译：数据处理系统至少包括第一和第二相关域，每个域包含至少一个处理单元，耦合第一和第二相干域的互连结构以及第一相干域内的高速缓冲存储器。高速缓冲存储器包括数据阵列，数据阵列的内容的高速缓存目录以及包括预取预测器的高速缓存控制器。预取预测器基于具有不同的第二目标地址的先前的第二预取操作的范围来确定具有第一目标地址的第一预取操作的互连结构上的广播的预测范围。高速缓存控制器以预测的范围在互连结构上发出第一个预取操作。

32. 发明授权

US08489807B2 Techniques for performing refresh operations in high-density memories 失效
标题翻译：在高密度存储器中执行刷新操作的技术
公开(公告)号：US08489807B2
公开(公告)日：2013-07-16
申请号：US12959637
申请日：2010-12-03
申请人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
发明人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40603
摘要： Techniques for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.
摘要翻译：公开了用于执行刷新操作的技术。响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

33. 发明申请

US20120144105A1 Method and Apparatus for Performing Refresh Operations in High-Density Memories 失效
标题翻译：在高密度记忆体中执行刷新操作的方法和装置
公开(公告)号：US20120144105A1
公开(公告)日：2012-06-07
申请号：US12959637
申请日：2010-12-03
申请人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
发明人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40603
摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.
摘要翻译：公开了一种执行刷新操作的方法。响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

34. 发明授权

US07734876B2 Protecting ownership transfer with non-uniform protection windows 失效
标题翻译：用不均匀的保护窗保护所有权转让
公开(公告)号：US07734876B2
公开(公告)日：2010-06-08
申请号：US11560603
申请日：2006-11-16
申请人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0833
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure indicates a duration of a protection window extension for each of the plurality of agents. Each protection window extension is a period following receipt of a combined response during which an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. Each of the plurality of agents is configured with a duration of a protection window extension by reference to the data structure, and at least two of the agents have protection window extensions of differing durations. The plurality of agents thereafter employ the configured protection window extensions.
摘要翻译：在数据处理系统中，多个代理之间进行通信。每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。在数据处理系统中的数据存储中，数据结构指示多个代理中的每一个的保护窗口扩展的持续时间。每个保护窗口扩展是接收到组合响应之后的周期，在该周期期间，所述多个代理中的相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。通过参考数据结构，多个代理中的每一个配置有保护窗口扩展的持续时间，并且至少两个代理具有不同持续时间的保护窗口扩展。此后，多个代理程序采用配置的保护窗口扩展。

35. 发明授权

US07454578B2 Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory 有权
标题翻译：数据处理系统和方法，用于使用存储器的位置预测性地选择操作的广播范围
公开(公告)号：US07454578B2
公开(公告)日：2008-11-18
申请号：US11055697
申请日：2005-02-10
申请人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译：高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。

36. 发明授权

US07444494B2 Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction 失效
标题翻译：用于使用基于历史的预测来预测性地选择操作的广播范围的数据处理系统和方法
公开(公告)号：US07444494B2
公开(公告)日：2008-10-28
申请号：US11140821
申请日：2005-05-31
申请人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0833 , G06F2212/507
摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
摘要翻译：根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。通过参考预测器预测性地选择后续操作的广播范围。

37. 发明授权

US08775904B2 Efficient storage of meta-bits within a system memory 有权
标题翻译：元位在系统存储器内的高效存储
公开(公告)号：US08775904B2
公开(公告)日：2014-07-08
申请号：US13313364
申请日：2011-12-07
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G11C29/42 , G06F11/10 , G11C29/54 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.
摘要翻译：提供了用于在系统存储器内有效存储元位的机制。这些机制将L / G位和SUE位组合以形成元位。机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。机制执行错误处理，而不管请求是否在全球重新发布。

38. 发明授权

US07818388B2 Data processing system, method and interconnect fabric supporting multiple planes of processing nodes 有权
标题翻译：支持多个处理节点平面的数据处理系统，方法和互连结构
公开(公告)号：US07818388B2
公开(公告)日：2010-10-19
申请号：US11245887
申请日：2005-10-07
申请人： Ravi K. Arimilli , Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke
发明人： Ravi K. Arimilli , Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
摘要翻译：数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。数据处理系统还包括多个点对点第一层链路。第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于通讯。数据处理系统还包括多个点到点第二层链路。所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元，并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。

39. 发明授权

US07627738B2 Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another node 失效
标题翻译：向耦合到节点内的其他处理器并耦合到另一节点中的相应处理器的处理器的请求和组合响应广播
公开(公告)号：US07627738B2
公开(公告)日：2009-12-01
申请号：US11960283
申请日：2007-12-19
申请人： Vicente E. Chung , Benjiman L. Goodman , Praveen S. Reddy , William J. Starke
发明人： Vicente E. Chung , Benjiman L. Goodman , Praveen S. Reddy , William J. Starke
IPC分类号： G06F15/163
CPC分类号： G06F15/17337
摘要： A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each of the plurality of first processing units is coupled to a respective one of the plurality of second processing units in the second processing node by a respective one of a plurality of point-to-point links.
摘要翻译：数据处理系统包括第一处理节点和第二处理节点。第一处理节点包括彼此耦合以进行通信的多个第一处理单元，并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。多个第一处理单元中的每个通过多个点对点链接中的相应一个耦合到第二处理节点中的多个第二处理单元中的相应一个。

40. 发明申请

US20130151790A1 Efficient Storage of Meta-Bits Within a System Memory 失效
公开(公告)号：US20130151790A1
公开(公告)日：2013-06-13
申请号：US13611909
申请日：2012-09-12
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G06F12/08
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

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