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31. 发明授权

US07328377B1 Error correction for programmable logic integrated circuits 有权
标题翻译：可编程逻辑集成电路的误差校正
公开(公告)号：US07328377B1
公开(公告)日：2008-02-05
申请号：US10766464
申请日：2004-01-27
申请人： David Lewis , Vaughn Betz
发明人： David Lewis , Vaughn Betz
IPC分类号： G06F11/00
CPC分类号： G06F11/106
摘要： Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into the memory cell. In another embodiment, regions of memory cells in a programmable logic IC each have associated error correcting circuitry which operates to continuously detect and correct errors as they occur. Error correcting circuitry can further be designed to reduce static hazards. It may be more desirable to design programmable logic IC routing architectures that reduce the number of memory cells needed to implement a given function. Error correcting circuitry can be provided for configuration memory or for an embedded memory block on a programmable logic IC.
摘要翻译：提供了用于检测和校正可编程逻辑IC中的错误的系统和方法。在一个实施例中，洗涤器周期性地读取可编程逻辑IC中的存储器单元，检测和校正任何错误，并将校正的内容写入存储单元。在另一个实施例中，可编程逻辑IC中的存储器单元的区域各自具有相关联的误差校正电路，其操作以在错误发生时连续地检测和校正错误。误差校正电路可进一步设计，以减少静电危害。可能更需要设计可编程逻辑IC路由架构，减少实现给定功能所需的存储器单元的数量。可以为配置存储器或可编程逻辑IC上的嵌入式存储器块提供纠错电路。

32. 发明授权

US07205791B1 Bypass-able carry chain in a programmable logic device 有权
标题翻译：可编程逻辑器件中的旁路携带链
公开(公告)号：US07205791B1
公开(公告)日：2007-04-17
申请号：US10799872
申请日：2004-03-12
申请人： Andy L. Lee , Ninh Ngo , Vaughn Betz , David Lewis , Bruce Pederson , James Schleicher
发明人： Andy L. Lee , Ninh Ngo , Vaughn Betz , David Lewis , Bruce Pederson , James Schleicher
IPC分类号： H03K19/173
CPC分类号： H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17764 , H03K19/17796
摘要： A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set of logic elements in the logic array block. The carry chain also includes a second path connecting a second series of logic elements in the logic array block, where one or more of the logic elements in the second series are not in the first series.
摘要翻译：逻辑阵列块中的进位链包括连接逻辑阵列块中的第一系列逻辑元件的第一路径，其中第一系列中的逻辑元件是逻辑阵列块中逻辑元件组的子集。进位链还包括连接逻辑阵列块中的第二系列逻辑元件的第二路径，其中第二系列中的一个或多个逻辑元件不在第一系列中。

33. 发明申请

US20090224800A1 PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS 有权
标题翻译：用于柔性布置IP功能块的PLD架构
公开(公告)号：US20090224800A1
公开(公告)日：2009-09-10
申请号：US12465464
申请日：2009-05-13
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

34. 发明授权

US07058920B2 Methods for designing PLD architectures for flexible placement of IP function blocks 失效
标题翻译：设计用于灵活放置IP功能块的PLD架构的方法
公开(公告)号：US07058920B2
公开(公告)日：2006-06-06
申请号：US10460685
申请日：2003-06-11
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

35. 发明授权

US06605962B2 PLD architecture for flexible placement of IP function blocks 有权
公开(公告)号：US06605962B2
公开(公告)日：2003-08-12
申请号：US10057442
申请日：2002-01-25
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

36. 发明授权

US07253660B1 Multiplexing device including a hardwired multiplexer in a programmable logic device 有权
标题翻译：多路复用器件包括可编程逻辑器件中的硬连线多路复用器
公开(公告)号：US07253660B1
公开(公告)日：2007-08-07
申请号：US10305886
申请日：2002-11-27
申请人： Paul Leventis , Bruce Pedersen , Chris Lane , Srinivas Reddy , David Lewis
发明人： Paul Leventis , Bruce Pedersen , Chris Lane , Srinivas Reddy , David Lewis
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K17/002
摘要： A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.
摘要翻译：描述多路复用装置。在一个实施例中，多路复用装置包括：硬连线多路复用器，包括多个输入端; 多个选择端子; 以及至少一个输出端子，其中多个输入端子耦合到多个块输入线或多个功能元件输入端子。在一个实施例中，多个输入端子被硬连线到多个块输入线或多个功能元件输入端子。在一个实施例中，多个选择端子耦合到第二多个功能元件输入端子或多个功能元件输出端子。在一个实施例中，多个块输入线包括多个逻辑阵列块（LAB）线，多个功能元件输入端包括多个逻辑元件（LE）输入端，多个功能元件输出端包括 LE输出端子。在另一实施例中，多路复用装置包括：硬连线多路复用器，包括多个数据信号输入端; 以及包括第一多个LE输出端子的第一多个LE，其中所述多个数据信号输入端子耦合到所述第一多个LE输出端子。

37. 发明授权

US07644386B1 Redundancy structures and methods in a programmable logic device 失效
标题翻译：可编程逻辑器件中的冗余结构和方法
公开(公告)号：US07644386B1
公开(公告)日：2010-01-05
申请号：US11623903
申请日：2007-01-17
申请人： Michael Chan , Paul Leventis , David Lewis , Ketan Zaveri , Hyun Mo Yi , Chris Lane
发明人： Michael Chan , Paul Leventis , David Lewis , Ketan Zaveri , Hyun Mo Yi , Chris Lane
IPC分类号： G06F17/50
CPC分类号： H03K19/17764 , H03K19/17736
摘要： An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
摘要翻译：本发明的实施例提供了一种可编程逻辑器件（“PLD”），其包括适于经由第一或第二交错垂直线选择性路由信号的冗余架构。其他实施例提供用于确定路由选择的配置逻辑和程序。其他实施例提供从相同行驱动的垂直线的近似分组。其他实施例提供了一旦有缺陷的行位置是已知的备用行位置的定义。

38. 发明授权

US07236633B1 Data compression and decompression techniques for programmable circuits 有权
标题翻译：可编程电路的数据压缩和解压缩技术
公开(公告)号：US07236633B1
公开(公告)日：2007-06-26
申请号：US10394472
申请日：2003-03-21
申请人： David Lewis , Paul Leventis
发明人： David Lewis , Paul Leventis
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H03M7/30
摘要： The present invention provides techniques for compressing and decompressing data in a programmable circuit. Programmable circuits can be configured according to user design by configuration data. Configuration data is compressed using a compression algorithm to save memory space. When the configuration data is needed, the compressed configuration data is decompressed using a decompressor. A decompressor can decompress configuration data using a variety of decompression algorithms such as arithmetic decoding. In an arithmetic encoding algorithm, symbol probabilities are used to increase compression of the data. The symbol probabilities can be transferred in a header of the encoded data stream and subsequently stored in a symbol probability table. The input of the decompressor may be coupled to a FIFO that temporarily stores the encoded data until it can be used by the decompressor.
摘要翻译：本发明提供了用于在可编程电路中压缩和解压缩数据的技术。可根据用户设计的配置数据配置可编程电路。使用压缩算法对配置数据进行压缩，以节省内存空间。当需要配置数据时，使用解压缩器对压缩的配置数据进行解压缩。解压缩器可以使用诸如算术解码的各种解压缩算法解压缩配置数据。在算术编码算法中，使用符号概率来增加数据的压缩。符号概率可以在编码数据流的报头中传送并随后存储在符号概率表中。解压缩器的输入可以耦合到临时存储编码数据的FIFO，直到解压缩器可以使用它。

39. 发明授权

US08201129B2 PLD architecture for flexible placement of IP function blocks 有权
标题翻译：用于灵活放置IP功能块的PLD架构
公开(公告)号：US08201129B2
公开(公告)日：2012-06-12
申请号：US12465464
申请日：2009-05-13
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： G06F17/50 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

40. 发明授权

US08191025B1 Redundancy structures and methods in a programmable logic device 有权
标题翻译：可编程逻辑器件中的冗余结构和方法
公开(公告)号：US08191025B1
公开(公告)日：2012-05-29
申请号：US12552214
申请日：2009-09-01
申请人： Michael Chan , Paul Leventis , David Lewis , Ketan Zaveri , Hyun Mo Yi , Chris Lane
发明人： Michael Chan , Paul Leventis , David Lewis , Ketan Zaveri , Hyun Mo Yi , Chris Lane
IPC分类号： G06F17/50 , G06F9/00 , G06F15/177 , H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , H03K19/17736
摘要： An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
摘要翻译：本发明的实施例提供了一种可编程逻辑器件（“PLD”），其包括适于经由第一或第二交错垂直线选择性路由信号的冗余架构。其他实施例提供用于确定路由选择的配置逻辑和程序。其他实施例提供从相同行驱动的垂直线的近似分组。其他实施例提供了一旦有缺陷的行位置是已知的备用行位置的定义。

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