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31. 发明授权

US5941977A Apparatus for handling register windows in an out-of-order processor 失效
标题翻译：用于处理乱序处理器中的寄存器窗口的装置
公开(公告)号：US5941977A
公开(公告)日：1999-08-24
申请号：US882220
申请日：1997-06-25
申请人： Ramesh Panwar , Dani Y. Dakhil
发明人： Ramesh Panwar , Dani Y. Dakhil
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F15/00
CPC分类号： G06F9/3863 , G06F9/30098 , G06F9/30101 , G06F9/30127 , G06F9/3842 , G06F9/462
摘要： In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.
摘要翻译：在推测性地执行指定逻辑地址的指令的处理器中，用于将逻辑地址推测地转换成物理地址的方法和装置。处理器具有可在寄存器文件内移动的寄存器窗口，保持与寄存器文件中窗口的位置对应的值的窗口指针寄存器，保持窗口指针寄存器的推测值的推测窗口指针寄存器。控制器识别期望修改窗口指针寄存器中的值的指令，并且响应于识别指令，控制器修改推测值。耦合到推测窗口指针寄存器的映射器根据包含在推测窗口指针寄存器中的推测值将指令指定的逻辑地址转换为物理地址。

32. 发明授权

US5854761A Cache memory array which stores two-way set associative data 失效
标题翻译：存储双向组关联数据的缓存存储器阵列
公开(公告)号：US5854761A
公开(公告)日：1998-12-29
申请号：US883544
申请日：1997-06-26
申请人： Sanjay Patel , Rajasekhar Cherabuddi , Ramesh Panwar , Adam R. Talcott
发明人： Sanjay Patel , Rajasekhar Cherabuddi , Ramesh Panwar , Adam R. Talcott
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10
CPC分类号： G11C7/00 , G06F12/0864 , G06F12/0886 , G11C7/1042
摘要： A cache memory array stores two-way set associative data. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set associative data, where the two ways of each even number set are aligned horizontally within the even set data bank. Also, the odd set data bank is aligned horizontally with the even set data bank such that each odd number set is aligned horizontally with a next even number set. The horizontally aligned ways are interleaved for data path width reduction. Set and way selection circuits extract lines of data from the array. The array may be structurally implemented by single-ported RAM cells.
摘要翻译：缓存存储器阵列存储双向组关联数据。奇数组数据组存储奇数组合的双向组关联数据，其中每个奇数组的两种方式在奇数组数据库内水平排列。偶数集数据库存储偶数集合的双向组关联数据，其中每个偶数集合的两个方式在偶数集数据库内水平对准。此外，奇数组数据组与偶数组数据组水平对准，使得每个奇数组都与下一个偶数组水平对准。水平对齐的方式被交织以减少数据路径宽度。设置和路径选择电路从数组中提取数据行。阵列可以在结构上由单端口RAM单元实现。

33. 发明授权

US08675648B1 Methods and apparatus for compression in packet classification 有权
标题翻译：分组分类中的压缩方法和装置
公开(公告)号：US08675648B1
公开(公告)日：2014-03-18
申请号：US12242143
申请日：2008-09-30
申请人： Deepak Goel , Ramesh Panwar , Srinivasan Jagannadhan
发明人： Deepak Goel , Ramesh Panwar , Srinivasan Jagannadhan
IPC分类号： H04L12/28
CPC分类号： H04L49/10
摘要： In one embodiment, a method includes receiving a policy vectors associated with a switch fabric, determining a compression scheme, and producing a compressed vector based on the policy vector and the compression scheme. The policy vector is represented by a bit sequence and has a plurality of policy bit values. A policy bit value from the plurality of policy bit vales is configured to trigger an action associated with a data packet in the switch fabric. The compression scheme is determined based on a portion of the policy vector.
摘要翻译：在一个实施例中，一种方法包括接收与交换结构相关联的策略向量，确定压缩方案，以及基于策略向量和压缩方案产生压缩向量。策略向量由比特序列表示，并具有多个策略比特值。来自多个策略比特值的策略比特值被配置为触发与交换结构中的数据分组相关联的动作。基于策略向量的一部分来确定压缩方案。

34. 发明授权

US08571023B2 Methods and Apparatus Related to Packet Classification Based on Range Values 有权
标题翻译：基于范围值的分组分类相关方法与设备
公开(公告)号：US08571023B2
公开(公告)日：2013-10-29
申请号：US12794175
申请日：2010-06-04
申请人： Ramesh Panwar , Deepak Goel , Srinivasan Jagannadhan
发明人： Ramesh Panwar , Deepak Goel , Srinivasan Jagannadhan
IPC分类号： H04L12/28 , H04J1/16
CPC分类号： H04L45/745 , H04L49/1515 , H04L49/3009
摘要： In one embodiment, an apparatus comprises a range selection module, a first stage of bloom filters, a second stage of bloom filters and a hashing module. The range selection module is configured to define a set of hash key vectors based on a set of range values associated with at least a portion of an address value from a data packet received at a multi-stage switch. The first stage of bloom filters and the second stage of bloom filters are collectively configured to determine that at least a portion of a hash key vector from the set of hash key vectors has a probability of being included in a hash table. The hashing module is configured to produce a hash value based on the hash key vector such that a first policy vector is selected based on the hash value and the first policy vector is decompressed to produce a second policy vector associated with the data packet.
摘要翻译：在一个实施例中，一种装置包括范围选择模块，第一阶段的布隆过滤器，第二阶段的布隆过滤器和散列模块。范围选择模块被配置为基于与在多级交换机处接收的数据分组的地址值的至少一部分相关联的一组范围值来定义一组散列密钥向量。布隆过滤器的第一阶段和布隆过滤器的第二阶段共同配置为确定来自该组散列密钥向量的散列密钥向量的至少一部分具有被包括在散列表中的概率。散列模块被配置为基于散列密钥向量产生散列值，使得基于散列值选择第一策略向量，并且解压缩第一策略向量以产生与数据分组相关联的第二策略向量。

35. 发明授权

US07966442B1 Cache using perfect hash function 有权
标题翻译：缓存使用完美的哈希函数
公开(公告)号：US07966442B1
公开(公告)日：2011-06-21
申请号：US12781612
申请日：2010-05-17
申请人： Ramesh Panwar , Philip A. Thomas
发明人： Ramesh Panwar , Philip A. Thomas
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0864 , Y02D10/13
摘要： In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing device. That is, the associative cache implements a fully associative map between a predetermined set of addresses and data values, employing only a single tag fetch comparison.
摘要翻译：通常，本公开描述了将数据存储在计算设备的高速缓存中并从中检索数据的技术。更具体地，描述了利用“完美散列”功能来实现计算设备内的关联高速缓存的技术。也就是说，相关高速缓存在一个预定的地址集合和数据值之间实现完全关联的映射，仅使用一个标签提取比较。

36. 发明授权

US07738454B1 Methods and apparatus related to packet classification based on range values 有权
标题翻译：基于范围值的与分组分类相关的方法和设备
公开(公告)号：US07738454B1
公开(公告)日：2010-06-15
申请号：US12242154
申请日：2008-09-30
申请人： Ramesh Panwar , Deepak Goel , Srinivasan Jagannadhan
发明人： Ramesh Panwar , Deepak Goel , Srinivasan Jagannadhan
IPC分类号： H04L12/28
CPC分类号： H04L45/745 , H04L49/1515 , H04L49/3009
摘要： In one embodiment, a method includes receiving a portion of a hash key vector. The hash key vector can be defined based on a range value and based on at least a portion of an address value from a data packet queued within a multi-stage switch. The method also includes defining, based on the hash key vector, a hash value associated with a location in a hash table when the portion of the hash key vector matches a bit vector stored in a tag table.
摘要翻译：在一个实施例中，一种方法包括接收散列密钥向量的一部分。可以基于范围值并且基于来自在多级交换机内排队的数据分组的地址值的至少一部分来定义散列密钥向量。该方法还包括当哈希密钥向量的一部分与存储在标签表中的位向量匹配时，基于散列密钥向量定义与散列表中的位置相关联的哈希值。

37. 发明申请

US20080271141A1 PARALLELIZED PATTERN MATCHING USING NON-DETERMINISTIC FINITE AUTOMATA 有权
标题翻译：使用非确定性有限自动机的并行模式匹配
公开(公告)号：US20080271141A1
公开(公告)日：2008-10-30
申请号：US11739365
申请日：2007-04-24
申请人： Gary Goldman , Philip A. Thomas , Ramesh Panwar
发明人： Gary Goldman , Philip A. Thomas , Ramesh Panwar
IPC分类号： G06F11/00
CPC分类号： H04L63/0245 , H04L63/1416
摘要： This disclosure describes techniques of determining whether a symbol stream includes a pattern defined by a regular expression. As described herein, the regular expression may be represented using a non-deterministic finite automaton (NFA). A plurality of states in the NFA may be evaluated in parallel. These states may be associated with a plurality of symbol positions in a symbol stream. Evaluating a plurality of states and symbols in parallel may allow for faster determinations of whether the symbol stream includes the pattern defined by the regular expression.
摘要翻译：本公开描述了确定符号流是否包括由正则表达式定义的模式的技术。如本文所述，正则表达式可以使用非确定性有限自动机（NFA）来表示。可以并行评估NFA中的多个状态。这些状态可以与符号流中的多个符号位置相关联。并行地评估多个状态和符号可以允许更快地确定符号流是否包括由正则表达式定义的模式。

38. 发明授权

US06154812A Method for inhibiting thrashing in a multi-level non-blocking cache system 失效
标题翻译：在多级非阻塞缓存系统中抑制抖动的方法
公开(公告)号：US06154812A
公开(公告)日：2000-11-28
申请号：US881725
申请日：1997-06-25
申请人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
发明人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.
摘要翻译：与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的设备接收数据访问的第一非阻塞缓存。第二非阻塞高速缓存耦合到第一非阻塞高速缓存以服务第一非阻塞高速缓存中的未命中。耦合到第二非阻塞缓存的数据返回路径将从第二非阻塞高速缓存返回的数据与第一非阻塞高速缓存和产生对第一非阻塞高速缓存的访问的设备耦合。

39. 发明授权

US6144982A Pipeline processor and computing system including an apparatus for tracking pipeline resources 失效
标题翻译：管道处理器和计算系统包括用于跟踪管道资源的设备
公开(公告)号：US6144982A
公开(公告)日：2000-11-07
申请号：US881731
申请日：1997-06-25
申请人： Ramesh Panwar
发明人： Ramesh Panwar
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： An apparatus for tracking pipeline resources of a processor involves fetching selected ones of the coded instructions and marking the fetched instructions with instruction metadata. The instruction metadata indicates a number of pipeline resources required by each instruction. The marked instructions are issued from the fetch unit and, using the instruction metadata, a count of a number of resources committed to issued instructions in the execution pipelines is maintained. When it is determined that the number of resources committed to issued instructions exceeds a preselected maximum and instructions are prevented from issuing from the fetch unit. As each instruction is retired, the instruction metadata is used to determine a number of resources released by retirement of the issued instruction.
摘要翻译：用于跟踪处理器的流水线资源的装置涉及取出编码指令中的选定的指令，并用指令元数据标记所取得的指令。指令元数据指示每个指令所需的流水线资源的数量。标记的指令是从提取单元发出的，并且使用指令元数据来维持在执行流水线中提交给发出的指令的资源的数量。当确定提交给发出的指令的资源的数量超过预选的最大值时，并且阻止指令从取出单元发出。当每个指令退出时，指令元数据用于确定通过退出指令释放的资源数量。

40. 发明授权

US6098165A Fetching and handling a bundle of instructions comprising instructions and non-complex instructions 失效
标题翻译：获取和处理包括指令和非复杂指令的一组指令
公开(公告)号：US6098165A
公开(公告)日：2000-08-01
申请号：US881908
申请日：1997-06-25
申请人： Ramesh Panwar , Dani Y. Dakhil
发明人： Ramesh Panwar , Dani Y. Dakhil
IPC分类号： G06F9/318 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3017 , G06F9/3867
摘要： In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by providing a by-passable helper logic for expanding complex instructions into microinstructions. Control logic parses a bundle of instructions into sub-bundles of non-complex instructions and sub-bundles of microinstructions. The control logic detects when a complex instruction is present in a bundle of instructions and directs the complex instruction to the helper logic for expansion into two or more microinstructions. Each non-complex instruction bypasses the helper logic, thereby improving the execution performance of the non-complex instruction.
摘要翻译：在执行复杂指令的处理器中，这些指令被扩展为微指令，非复杂指令执行通过提供用于将复杂指令扩展为微指令的旁路辅助逻辑来优化。控制逻辑将一束指令解析成非复杂指令和微指令子束的子束。控制逻辑检测何时在一组指令中存在复杂指令，并将复杂指令引导到辅助逻辑以扩展成两个或多个微指令。每个非复杂指令绕过辅助逻辑，从而提高非复杂指令的执行性能。

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