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31. 发明授权

US06594609B1 Scan vector support for event based test system 失效
标题翻译：扫描向量支持基于事件的测试系统
公开(公告)号：US06594609B1
公开(公告)日：2003-07-15
申请号：US09721828
申请日：2000-11-25
申请人： Anthony Le , Rochit Rajsuman
发明人： Anthony Le , Rochit Rajsuman
IPC分类号： G01R3100
CPC分类号： G01R31/31924 , G01R31/31917
摘要： An event based test system can generate scan vectors for testing a semiconductor device of scan design without requiring a large amount of scan memory. The test system includes an event memory for storing timing data and event type data of each event where the timing data is expressed by N data bits for defining one test vector, an event generator for generating an event with use of the timing data and the event type data, and a mode change circuit provided between the event memory and the event generator for changing signal paths between a normal mode for generating the test vectors and a scan mode for generating the scan vectors. In the test system, each bit of the N data bits in the event memory defines 2N scan vectors which are provided to the event generator in a series fashion, thereby producing the 2N scan vectors at each access of the event memory.
摘要翻译：基于事件的测试系统可以生成用于测试扫描设计的半导体器件的扫描向量，而不需要大量的扫描存储器。测试系统包括事件存储器，用于存储每个事件的定时数据和事件类型数据，其中定时数据由用于定义一个测试向量的N个数据位表示，用于使用定时数据和事件来生成事件的事件发生器以及设置在事件存储器和事件发生器之间的模式改变电路，用于在用于产生测试矢量的正常模式和用于产生扫描矢量的扫描模式之间改变信号路径。在测试系统中，事件存储器中的N个数据位的每个位定义2N个扫描向量，这些扫描向量以串联方式提供给事件发生器，从而在事件存储器的每次访问期间产生2N个扫描向量。

32. 发明授权

US06578169B1 Data failure memory compaction for semiconductor test system 失效
标题翻译：半导体测试系统的数据故障记忆压缩
公开(公告)号：US06578169B1
公开(公告)日：2003-06-10
申请号：US09545730
申请日：2000-04-08
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3128
CPC分类号： G01R31/31935 , G11C29/56
摘要： A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.
摘要翻译：用于测试被测半导体器件（DUT）的半导体测试系统能够将故障数据存储在具有小存储器容量的数据故障存储器中。半导体测试系统包括用于在其中存储模式数据以产生要提供给DUT的测试模式的模式存储器，用于评估DUT的输出信号的装置和当其中存在故障时产生故障数据的装置，用于存储故障数据，以及压缩装置，用于在第一测试操作中将模式存储器的多个地址分配给数据故障存储器的单个地址，使得针对模式存储器的每组地址发生的故障数据被存储在数据故障存储器的对应地址，以及仅针对其中检测到故障数据而不进行地址压缩的模式存储器的一组地址执行第二测试操作。

33. 发明授权

US06377065B1 Glitch detection for semiconductor test system 失效
标题翻译：半导体测试系统的毛刺检测
公开(公告)号：US06377065B1
公开(公告)日：2002-04-23
申请号：US09548875
申请日：2000-04-13
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3126
CPC分类号： G01R31/31937 , G01R31/31922
摘要： A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT) . The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.
摘要翻译：半导体测试系统具有毛刺检测功能，用于检测来自被测器件的输出信号中的毛刺，以准确地评估待测器件（DUT）。半导体测试系统包括用于存储事件数据的事件存储器，用于产生测试图案的事件发生器，用于产生来自事件存储器的事件数据的选通信号和预期模式，用于将测试模式从事件发生器发送到 DUT并接收DUT的输出信号，并通过选通信号的定时对输出信号进行采样，用于将采样输出数据与预期模式进行比较的模式比较器，以及用于从DUT接收输出信号的检测单元通过对输出信号中的边缘数进行计数并比较预期的边缘数量来在输出信号中产生毛刺。

34. 发明授权

US06226765B1 Event based test system data memory compression 失效
标题翻译：基于事件的测试系统数据存储器压缩
公开(公告)号：US06226765B1
公开(公告)日：2001-05-01
申请号：US09259402
申请日：1999-02-26
申请人： Anthony Le , James Alan Turnquist
发明人： Anthony Le , James Alan Turnquist
IPC分类号： G11C2900
CPC分类号： G01R31/31921
摘要： An event based test system for storing event data in a compressed form to reduce the size of a memory and decompressing the data to produce the events for testing a device under test (DUT). The event based test system includes a clock count memory for storing clock count data of each event wherein the clock count data is formed of one or more data words depending on the value of the integral part data, a vernier data memory for storing vernier data of each event wherein the vernier data memory stores vernier data for two or more events in the same memory location, an address sequencer for generating address data for accessing the clock count memory and the vernier data memory, a decompressor for reproducing the clock count data from the clock count memory and the vernier data from the vernier data memory corresponding to each event. The event based test system may further include an event process controller for producing an overall delay time of each event relative to a predetermined reference point based on the clock count data and vernier data from the decompressor, and a fine delay controller for generating each event based on the overall delay time to produce test signals for testing the DUT.
摘要翻译：一种基于事件的测试系统，用于以压缩形式存储事件数据，以减小存储器的大小并解压缩数据，以产生用于测试被测器件（DUT）的事件。基于事件的测试系统包括时钟计数存储器，用于存储每个事件的时钟计数数据，其中时钟计数数据由取决于整数部分数据的值的一个或多个数据字形成，用于存储游标数据的游标数据的游标数据存储器每个事件其中游标数据存储器存储相同存储器位置中的两个或更多个事件的游标数据，用于产生用于访问时钟计数存储器和游标数据存储器的地址数据的地址定序器，用于从时钟计数存储器和对应于每个事件的游标数据存储器的游标数据。基于事件的测试系统还可以包括事件处理控制器，用于基于来自解压缩器的时钟计数数据和游标数据产生相对于预定参考点的每个事件的总延迟时间，以及用于产生每个事件的精细延迟控制器在产生用于测试DUT的测试信号的总延迟时间上。

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