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31. 发明授权

US06895462B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US06895462B2
公开(公告)日：2005-05-17
申请号：US10223242
申请日：2002-08-20
申请人： Carl Roger Pertry , Heiko Meyer , Thomas Schulz
发明人： Carl Roger Pertry , Heiko Meyer , Thomas Schulz
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F9/30101
摘要： An integrated circuit includes a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the processor and the modules is connected to a fast AMBA-AHB bus, several advantages are achieved: for one, faster access is possible to each register. For another, the placement of the registers and the routing for the registers is simplified. This in particular allows chip area to be saved, which leads to cost savings in manufacture and enables higher component density. Furthermore, a slow AMBA-APB bus has now become optional.
摘要翻译：集成电路包括处理器和至少一个模块，并提供模块所需的寄存器以及访问这些寄存器。通过将根据本发明的所需寄存器集中在中央寄存器组中，其类似于处理器和模块连接到快速AMBA-AHB总线，实现了几个优点：一个可以对每个寄存器进行更快的访问。另外，寄存器的放置和寄存器的路由也被简化了。这特别允许节省芯片面积，这导致制造成本节省并实现更高的组件密度。此外，慢AMBA-APB总线现在已经成为可选的。

32. 发明授权

US06459123B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06459123B1
公开(公告)日：2002-10-01
申请号：US09302768
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2994
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

33. 发明授权

US6141202A Method and apparatus for triggering a fuse 失效
标题翻译：用于触发保险丝的方法和装置
公开(公告)号：US6141202A
公开(公告)日：2000-10-31
申请号：US370264
申请日：1999-08-09
申请人： Rainer Maeckel , Thomas Schulz
发明人： Rainer Maeckel , Thomas Schulz
IPC分类号： B60R16/02 , B60R16/00 , H01H85/00 , H01H85/46 , H02H3/08 , H02H3/087 , H01H71/12 , H02H3/00
CPC分类号： H01H85/46 , H01H2085/466
摘要： The response time of a melting fuse is controlled or influenced by temporarily boosting a threshold level from a first constant value (I.sub.1) to a second dynamic value (I.sub.2) which is then caused to decay in a controlled manner during a fixed time between (t.sub.1) and (t.sub.2) and in accordance with a selectable decay function. If a current (m) flowing through the fuse exceeds the decaying threshold value a fuse blowing current is generated and supplied to the fuse, whereby the fuse blows sooner than it would have, if the excess current had prevailed for a long enough time between (t.sub.1) and (t.sub.X). On the other hand, the fuse does not blow in response to short duration transient excess currents that occur, for example at starting an engine. The engine start impulse which may be used to temporarily raise the threshold value from (I.sub.1) to (I.sub.2) and then cause said controlled decay.
摘要翻译：通过将阈值电平从第一恒定值（I1）暂时升高到第二动态值（I2）来控制或影响熔化熔丝的响应时间，然后在（t1）的固定时间内以受控的方式衰减）和（t2），并且根据可选择的衰减功能。如果流过保险丝的电流（m）超过衰减阈值，则产生保险丝熔断电流并将其提供给保险丝，如果过电流在（ t1）和（tX）。另一方面，例如在启动发动机时，保险丝不会发生短路瞬态过电流而发生故障。发动机起动脉冲可用于将阈值从（I1）暂时升高到（I2），然后引起所述受控衰减。

34. 发明申请

US20140034196A1 HOHERFESTER MEHRPHASENSTAHL MIT AUSGEZEICHNETEN UMFORMEIGENSCHAFTEN HIGH STRENGTH MULTI-PHASE STEEL HAVING EXCELLENT FORMING PROPERTIES 审中-公开
标题翻译： HOHERFESTER MEHRPHASENSTAHL MIT AUSGEZEICHNETEN UMFORMEIGENSCHAFTEN高强度多相钢具有优异的成型性能
公开(公告)号：US20140034196A1
公开(公告)日：2014-02-06
申请号：US13981870
申请日：2011-11-30
申请人： Andreas Wedemeier , Thomas Schulz , Michael Pohl , Phillip Wüllner , Jörg Heinecke , Christian Schlegel
发明人： Andreas Wedemeier , Thomas Schulz , Michael Pohl , Phillip Wüllner , Jörg Heinecke , Christian Schlegel
IPC分类号： C21D8/02 , C22C38/32 , C22C38/28 , C22C38/00 , C22C38/22 , C22C38/06 , C22C38/04 , C22C38/02 , C22C38/38 , C22C38/26
CPC分类号： C22C38/001 , C21D1/185 , C21D8/0226 , C21D8/0236 , C21D8/0247 , C21D2211/002 , C21D2211/005 , C22C1/02 , C22C38/00 , C22C38/02 , C22C38/04 , C22C38/06 , C22C38/22 , C22C38/26 , C22C38/28 , C22C38/32 , C22C38/38
摘要： The invention relates to a high strength multi-phase steel for a cold- or hot-rolled steel strip having excellent forming properties, in particular for light vehicle construction, comprising the elements (contents in mass %): C 0.060 to=0.115; Al 0.020 to=0.060; Si 0.100 to=0.500; Mn 1.300 to=2.500; P=0.025; S=0.0100; Cr 0.280 to=0.480; Mo
摘要翻译：本发明涉及一种用于冷或热轧钢带的高强度多相钢，具有优异的成形性能，特别是轻型车辆结构，其包含元素（质量％）：C 0.060至= 0.115; Al 0.020〜= 0.060; Si 0.100 = 0.500; Mn 1.300〜2.500; P = 0.025; S = 0.0100; Cr 0.280 = 0.480; Mo <0.150; Ti = 0.005〜0.050; Nb = 0.005〜0.050; B = 0.0005〜= 0.0060; N = 0.0100; 其余为铁，包括存在于钢中的通常元素，上面未提及。

35. 发明授权

US08604375B2 Device with at least one control element 有权
标题翻译：具有至少一个控制元件的设备
公开(公告)号：US08604375B2
公开(公告)日：2013-12-10
申请号：US12654975
申请日：2010-01-11
申请人： Georgy Yltchev , Thomas Schulz , Christian Doebele
发明人： Georgy Yltchev , Thomas Schulz , Christian Doebele
IPC分类号： H01H13/85
CPC分类号： H01H13/48 , H01H13/06 , H01H2205/016 , H01H2215/014 , H01H2223/002 , H01H2227/028
摘要： A device is provided with at least one control element that can be used to trigger a switching process for electrical or mechanical installations. The control element is positioned in a device housing for the device, such that the control element is designed as a snap disk, which is made of metal, and such that the snap disk has a rim which is connected to the device housing through material engagement and which forms a seal between the device housing and the control element, such that an area of the snap disk that borders the rim is designed as a reversibly deformable uncoupling area.
摘要翻译：设备具有至少一个可用于触发用于电气或机械安装的切换过程的控制元件。控制元件定位在用于装置的装置壳体中，使得控制元件被设计为由金属制成的卡盘，并且使得卡盘具有通过材料接合连接到装置壳体的边缘并且其在所述装置壳体和所述控制元件之间形成密封，使得所述卡盘与所述边缘相接合的区域被设计为可逆变形的解耦区域。

36. 发明授权

US08188551B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08188551B2
公开(公告)日：2012-05-29
申请号：US11240698
申请日：2005-09-30
申请人： Thomas Schulz , Hongfa Luan
发明人： Thomas Schulz , Hongfa Luan
IPC分类号： H01L29/76
CPC分类号： H01L27/1211 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L29/66803 , H01L29/785
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.
摘要翻译：公开了半导体器件及其制造方法。互补的金属氧化物半导体（CMOS）器件包括PMOS晶体管，其具有包括第一参数的至少两个第一栅电极和具有包括第二参数的至少两个第二栅电极的NMOS晶体管，其中第二参数不同于第一参数参数。第一参数和第二参数可以包括PMOS和NMOS晶体管的栅电极材料的厚度或掺杂物分布。至少两个第一栅电极和至少两个第二栅电极的第一和第二参数分别建立PMOS和NMOS晶体管的功函数。

37. 发明申请

US20120119297A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120119297A1
公开(公告)日：2012-05-17
申请号：US13355610
申请日：2012-01-23
申请人： Thomas Schulz
发明人： Thomas Schulz
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括形成晶体管，晶体管包括具有第一侧和与第一侧相对的第二侧的翅片。晶体管包括设置在鳍片的第一侧上的第一栅电极和设置在鳍片的第二侧上的第二栅电极。该方法包括在晶体管的第一栅电极和第二栅电极上形成金属的硅化物或锗化物。硅化物或锗化物的金属的量在靠近散热片的第一栅电极和第二栅电极上基本均匀。

38. 发明申请

US20110013668A1 SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION 审中-公开
标题翻译：半导体电路布置及相关的温度检测方法
公开(公告)号：US20110013668A1
公开(公告)日：2011-01-20
申请号：US12888528
申请日：2010-09-23
申请人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
发明人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
IPC分类号： G01K7/01 , H01L29/74 , H01L27/06
CPC分类号： G01K7/015 , H01L27/0727 , H01L27/1203 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.
摘要翻译：公开了半导体电路装置和温度检测方法。一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极实现场效应晶体管。在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层边区。

39. 发明授权

US07851844B2 Memory device having cross-shaped semiconductor fin structure 有权
标题翻译：存储器件具有十字形半导体鳍结构
公开(公告)号：US07851844B2
公开(公告)日：2010-12-14
申请号：US12013969
申请日：2008-01-14
申请人： Koen van der Zanden , Thomas Schulz
发明人： Koen van der Zanden , Thomas Schulz
IPC分类号： H01L29/788 , H01L29/792 , H01L21/3361
CPC分类号： H01L21/28273 , G11C16/0475 , G11C16/10 , H01L21/28282 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568
摘要： In an embodiment, a memory device, including: a semiconductor fin structure, each end portion of the fin structure including a source/drain region; a charge storage layer covering at least a portion of the fin structure; and a gate layer covering at least a portion of the charge storage layer.
摘要翻译：在一个实施例中，一种存储器件，包括：半导体鳍结构，鳍结构的每个端部包括源/漏区; 覆盖所述翅片结构的至少一部分的电荷存储层; 以及覆盖电荷存储层的至少一部分的栅极层。

40. 发明授权

US07820505B2 Integrated circuit arrangement with capacitor and fabrication method 有权
标题翻译：具有电容器的集成电路布置及其制造方法
公开(公告)号：US07820505B2
公开(公告)日：2010-10-26
申请号：US11862640
申请日：2007-09-27
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

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