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31. 发明申请

US20110101538A1 CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 失效
标题翻译：创造不同深度的VIAS和TRENCHES
公开(公告)号：US20110101538A1
公开(公告)日：2011-05-05
申请号：US12610624
申请日：2009-11-02
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
摘要翻译：本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。还提供了由此制成的半导体结构。

32. 发明申请

US20110084403A1 PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT 有权
标题翻译：使用自对准的衬垫进行粘合增强的PAD结合
公开(公告)号：US20110084403A1
公开(公告)日：2011-04-14
申请号：US12575980
申请日：2009-10-08
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/05007 , H01L2224/05014 , H01L2224/0502 , H01L2224/05099 , H01L2224/05547 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/08121 , H01L2224/80001 , H01L2224/80345 , H01L2224/80357 , H01L2224/80359 , H01L2224/80895 , H01L2224/80896 , H01L2224/821 , H01L2224/9212 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/1305 , H01L2924/1306 , H01L2924/00 , H01L2224/80 , H01L2224/82
摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.
摘要翻译：将两个基材放在一起并放置在电镀浴中。在一个实施例中，将导电材料电镀在存在于第一金属焊盘和第二金属焊盘之间的界面处的微观空腔中，以形成粘附到第一金属焊盘的表面的至少一个界面电镀金属衬垫部分，第二个金属垫。在另一个实施例中，至少一个金属焊盘相对于电介质表面在被聚集之前是凹进的。将两个基板放置在电镀槽中，并且将导电材料镀在第一金属焊盘和第二金属焊盘之间的空腔中，以形成附着在第一金属焊盘的表面上的连续的电镀金属衬垫层，第二个金属垫。

33. 发明申请

US20090278258A1 INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME 有权
标题翻译：带有MUSHROOM型氧化物覆盖层的互连结构及其制造方法
公开(公告)号：US20090278258A1
公开(公告)日：2009-11-12
申请号：US12115944
申请日：2008-05-06
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.
摘要翻译：提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征。本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在第一电介质盖58。

34. 发明授权

US08946006B2 Replacement gate MOSFET with raised source and drain 有权
公开(公告)号：US08946006B2
公开(公告)日：2015-02-03
申请号：US12913922
申请日：2010-10-28
申请人： Shom Ponoth , David V. Horak , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Chih-Chao Yang
IPC分类号： H01L21/00 , H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/7834
摘要： A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.

35. 发明授权

US08835305B2 Method of fabricating a profile control in interconnect structures 有权
标题翻译：在互连结构中制作轮廓控制的方法
公开(公告)号：US08835305B2
公开(公告)日：2014-09-16
申请号：US13562953
申请日：2012-07-31
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
IPC分类号： H01L21/4763 , H01L23/12 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76813 , H01L21/76831 , H01L21/76844 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.
摘要翻译：可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

36. 发明授权

US08765585B2 Method of forming a borderless contact structure employing dual etch stop layers 失效
标题翻译：使用双蚀刻停止层形成无边界接触结构的方法
公开(公告)号：US08765585B2
公开(公告)日：2014-07-01
申请号：US13095955
申请日：2011-04-28
申请人： Su C. Fan , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Su C. Fan , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L21/336
CPC分类号： H01L29/78 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41775 , H01L29/66545
摘要： Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.
摘要翻译：形成在衬底上的每个栅极结构包括栅极电介质，栅极导体，第一蚀刻停止层和栅极盖电介质。在栅极结构，栅极间隔物以及源极和漏极区域上形成第二蚀刻停止层。在第二蚀刻停止层上方形成第一接触电介质层和第二接触电介质层。形成至少延伸到栅极盖电介质的顶表面的栅极接触通孔。随后形成延伸到第一和第二接触电介质层之间的界面的源极/漏极接触孔。通过同时蚀刻暴露的栅极帽电介质和第一接触电介质层的暴露部分，然后同时蚀刻第一和第二蚀刻停止层，使各种接触通孔垂直延伸。从而形成与外表面自对准的源极/漏极接触孔。

37. 发明申请

US20130307086A1 MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES 有权
标题翻译：工作功能的绝对保护功能材料部分在更换门电极
公开(公告)号：US20130307086A1
公开(公告)日：2013-11-21
申请号：US13471852
申请日：2012-05-15
申请人： Charles W. Koburger, III , Marc A. Bergendahl , David V. Horak , Shom Ponoth , Chih-Chao Yang
发明人： Charles W. Koburger, III , Marc A. Bergendahl , David V. Horak , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L29/401 , E21B43/305 , E21B47/122 , H01L21/823431 , H01L21/823456 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L27/1211
摘要： In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.
摘要翻译：在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。

38. 发明授权

US08525339B2 Hybrid copper interconnect structure and method of fabricating same 有权
标题翻译：混合铜互连结构及其制造方法
公开(公告)号：US08525339B2
公开(公告)日：2013-09-03
申请号：US13191999
申请日：2011-07-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76843 , H01L21/76847 , H01L21/76877 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.
摘要翻译：提供了包含在相同开口内具有不同杂质水平的铜区域的混合互连结构。在一个实施例中，互连结构包括具有位于其中的至少一个开口的图案化电介质材料。双材料衬垫至少位于所述至少一个开口内的图案化电介质材料的侧壁上。所述结构还包括具有位于所述至少一个开口的底部区域内的第一杂质水平的第一铜区域和具有位于所述至少一个开口的顶部区域内的第二杂质水平的第二铜区域和位于所述第一铜地区。根据本公开，第一铜区域的第一杂质水平不同于第二铜区域的第二杂质水平。

39. 发明授权

US08399350B2 Formation of air gap with protection of metal lines 失效
标题翻译：形成气隙，保护金属线
公开(公告)号：US08399350B2
公开(公告)日：2013-03-19
申请号：US12700792
申请日：2010-02-05
申请人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
发明人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L24/80 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295
摘要： Method for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer, and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask exposes a surface of only the second portion of the cap layer which has the greater height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer. Material can be removed from the dielectric layer where exposed to the etchant.
摘要翻译：一种在其电介质层中具有气隙的微电子元件的制造方法。可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并延伸第二高度高于介电层表面的高度，第二高度大于第一高度。在形成盖层之后，可以在盖层之上形成掩模。掩模仅暴露具有较大高度的盖层的第二部分的表面。随后，蚀刻剂可以被引导到盖层的第一和第二部分。材料可以从暴露于蚀刻剂的介电层去除。

40. 发明申请

US20130043556A1 SIZE-FILTERED MULTIMETAL STRUCTURES 审中-公开
标题翻译：尺寸过滤的多层结构
公开(公告)号：US20130043556A1
公开(公告)日：2013-02-21
申请号：US13211351
申请日：2011-08-17
申请人： David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L21/28 , H01L21/20 , H01L23/48
CPC分类号： H01L21/76877 , H01L23/5256 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
摘要翻译：尺寸过滤的金属互连结构允许形成具有不同组成的金属结构。在介电材料层中形成具有不同宽度的沟槽。保形材料层被共形沉积以完全填充具有小于阈值宽度的宽度的沟槽。执行各向同性蚀刻以去除宽沟槽中的阻挡材料层，即具有大于阈值宽度的宽度的沟槽，而窄沟槽（即，具有小于阈值宽度的宽度的沟槽）保持与所述阈值宽度的剩余部分阻挡材料层。宽沟槽用第一金属填充和平坦化，以形成具有大于临界宽度的宽度的第一金属结构。去除阻挡材料层的剩余部分以形成空腔，其中填充有第二金属以形成具有小于临界宽度的宽度的第二金属结构。

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