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31. 发明授权

US07951708B2 Copper interconnect structure with amorphous tantalum iridium diffusion barrier 有权
标题翻译：铜互连结构与非晶钽铱扩散屏障
公开(公告)号：US07951708B2
公开(公告)日：2011-05-31
申请号：US12477389
申请日：2009-06-03
申请人： Patrick W. DeHaven , Daniel C. Edelstein , Philip L. Flaitz , Takeshi Nogami , Stephen M. Rossnagel , Chih-Chao Yang
发明人： Patrick W. DeHaven , Daniel C. Edelstein , Philip L. Flaitz , Takeshi Nogami , Stephen M. Rossnagel , Chih-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/2855 , H01L21/76805 , H01L21/76807 , H01L21/76843 , H01L21/76844 , H01L21/76846 , Y10T428/24917
摘要： A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60 atomic % such that the barrier layer has a resulting amorphous structure.
摘要翻译：形成用于半导体器件制造的扩散阻挡层的方法包括通过物理气相沉积（PVD）工艺将沉积有铱掺杂的钽基阻挡层沉积在图案化层间电介质（ILD）层上，其中阻挡层被沉积其铱浓度至少为60原子％，使得阻挡层具有所得的无定形结构。

32. 发明授权

US07859113B2 Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method 有权
$Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method$
标题翻译：结构包括通过铜线上的难熔金属环和绝缘层无衬里界面及相关方法
公开(公告)号：US07859113B2
公开(公告)日：2010-12-28
申请号：US11679483
申请日：2007-02-27
申请人： Daniel C. Edelstein , Takeshi Nogami , Ping-Chuan Wang , Yun-Yu Wang , Chih-Chao Yang
发明人： Daniel C. Edelstein , Takeshi Nogami , Ping-Chuan Wang , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L21/76814 , H01L21/76805 , H01L21/76843 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface.
摘要翻译：公开了包括铜线处的难熔金属环和介电层无衬里界面的结构以及相关方法。在一个实施例中，一种结构包括具有与其上方的介电层无衬层界面的铜线; 从铜线向上延伸穿过介电层的通孔; 以及从所述通孔的一侧延伸并部分地沿着所述无衬里界面延伸的耐火金属套环。耐火金属轴环通过改善通孔周围的界面防止电迁移引起的狭缝空隙，并防止在通孔附近发生空隙成核。此外，难熔金属套环在通孔和介电层无衬里界面周围存在空隙的情况下提供电冗余。

33. 发明申请

US20100311236A1 COPPER INTERCONNECT STRUCTURE WITH AMORPHOUS TANTALUM IRIDIUM DIFFUSION BARRIER 有权
标题翻译：铜阳极结构与非晶态铁素体扩散阻挡层
公开(公告)号：US20100311236A1
公开(公告)日：2010-12-09
申请号：US12477389
申请日：2009-06-03
申请人： Patrick W. DeHaven , Daniel C. Edelstein , Philip L. Flaitz , Takeshi Nogami , Stephen M. Rossnagel , Chih-Chao Yang
发明人： Patrick W. DeHaven , Daniel C. Edelstein , Philip L. Flaitz , Takeshi Nogami , Stephen M. Rossnagel , Chih-Chao Yang
IPC分类号： H01L21/768 , B05D5/12 , B32B15/00 , B32B3/10
CPC分类号： H01L21/2855 , H01L21/76805 , H01L21/76807 , H01L21/76843 , H01L21/76844 , H01L21/76846 , Y10T428/24917
摘要： A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60% by atomic weight such that the barrier layer has a resulting amorphous structure.
摘要翻译：形成用于半导体器件制造的扩散阻挡层的方法包括通过物理气相沉积（PVD）工艺将沉积有铱掺杂的钽基阻挡层沉积在图案化层间电介质（ILD）层上，其中阻挡层被沉积其铱浓度至少为原子量的60％，使得阻挡层具有所得的无定形结构。

34. 发明授权

US07572682B2 Semiconductor structure for fuse and anti-fuse applications 失效
标题翻译：保险丝和反熔丝应用的半导体结构
公开(公告)号：US07572682B2
公开(公告)日：2009-08-11
申请号：US11755995
申请日：2007-05-31
申请人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
发明人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译：提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层第一厚度位于第一扩散阻挡层上。

35. 发明申请

US20090189287A1 NOBLE METAL CAP FOR INTERCONNECT STRUCTURES 有权
标题翻译：用于互连结构的NOBLE金属盖
公开(公告)号：US20090189287A1
公开(公告)日：2009-07-30
申请号：US12021316
申请日：2008-01-29
申请人： Chih-Chao Yang , Daniel C. Edelstein , Fenton R. McFeely
发明人： Chih-Chao Yang , Daniel C. Edelstein , Fenton R. McFeely
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76826 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.
摘要翻译：提供了包括具有约3.0或更小介电常数的介电材料的互连结构。该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料。电介质材料还具有在形成贵金属盖之前被制成疏水性的表面层。贵金属盖直接位于至少一个导电材料的上表面上。由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物沉积形式在该疏水电介质表面上。

36. 发明申请

US20090035954A1 INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME 有权
标题翻译：与颗粒生长促进层的互连结构及其形成方法
公开(公告)号：US20090035954A1
公开(公告)日：2009-02-05
申请号：US11831149
申请日：2007-07-31
申请人： Chih-Chao Yang , Daniel C. Edelstein
发明人： Chih-Chao Yang , Daniel C. Edelstein
IPC分类号： H01R12/00 , B05D5/12
CPC分类号： H01L21/76873 , H01L21/76805 , H01L21/76844 , H01L21/76847 , H01L21/76877
摘要： In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.
摘要翻译：通常，本发明提供一种互连结构及其形成方法。本发明公开了一种互连结构，其包括嵌入在扩散阻挡层和晶粒生长促进层之间的Cu籽晶层。具体地说，在本发明的范围内，在图案化的层间电介质层上形成扩散阻挡层。然后在扩散阻挡层上形成（Cu）接种层，并且在籽晶层上形成晶粒生长促进层。一旦形成了晶粒生长促进层，就进行后处理步骤（例如电镀和化学机械抛光）。

37. 发明申请

US20080315426A1 METAL CAP WITH ULTRA-LOW k DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS 有权
标题翻译：用于电路互连应用的具有超低k介电材料的金属盖
公开(公告)号：US20080315426A1
公开(公告)日：2008-12-25
申请号：US11766261
申请日：2007-06-21
申请人： Chih-Chao Yang , Daniel C. Edelstein
发明人： Chih-Chao Yang , Daniel C. Edelstein
IPC分类号： H01L23/538 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76885 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
摘要翻译：提供了一种互连结构，其具有增强的电迁移可靠性，而不降低电路短产量，并且提高了技术可扩展性。本发明的互连结构包括具有约3.0或更小的介电常数的电介质材料。电介质材料具有嵌入其中的至少一种导电材料。贵金属盖直接位于至少一个导电区域的上表面上。贵金属帽基本上不延伸到与至少一个导电区域相邻的电介质材料的上表面上，并且贵金属帽材料不会沉积在电介质表面上。还提供了利用低温（约300℃或更低）化学沉积工艺制造这种互连结构的方法。

38. 发明申请

US20080179660A1 CONTACT FORMING METHOD AND RELATED SEMICONDUCTOR DEVICE 有权
标题翻译：联系形成方法和相关半导体器件
公开(公告)号：US20080179660A1
公开(公告)日：2008-07-31
申请号：US11668717
申请日：2007-01-30
申请人： Daniel C. Edelstein , Louis Lu-Chen Hsu , Chih-Chao Yang
发明人： Daniel C. Edelstein , Louis Lu-Chen Hsu , Chih-Chao Yang
IPC分类号： H01L29/78 , H01L21/28 , H01L21/4763
CPC分类号： H01L21/76829 , H01L21/76831 , H01L29/6653 , H01L29/78
摘要： Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).
摘要翻译：公开了触点形成方法和相关的半导体器件。一种方法包括在结构和衬底上形成第一衬里，第一衬套覆盖结构的侧壁; 在所述第一衬垫和所述结构上形成介电层; 在所述介电层中形成与所述第一衬垫的接触孔; 在所述接触孔中形成第二衬垫，包括覆盖所述侧壁的所述第一衬套上方; 在接触孔的底部移除第一和第二衬垫; 并用导电材料填充接触孔以形成接触。结构侧壁上较厚的衬套防止短路，并允许至少保持一个或多个衬套中的任何固有应力。

39. 发明申请

US20130043591A1 TUNGSTEN METALLIZATION: STRUCTURE AND FABRICATION OF SAME 失效
公开(公告)号：US20130043591A1
公开(公告)日：2013-02-21
申请号：US13211722
申请日：2011-08-17
申请人： Chih-Chao Yang , Daniel C. Edelstein
发明人： Chih-Chao Yang , Daniel C. Edelstein
IPC分类号： H01L23/482 , H01L21/283
CPC分类号： H01L21/76838 , H01L21/76814 , H01L21/76831 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76885 , H01L21/76895
摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

40. 发明申请

US20130000962A1 FORMATION OF ALLOY LINER BY REACTION OF DIFFUSION BARRIER AND SEED LAYER FOR INTERCONNECT APPLICATION 有权
标题翻译：通过扩散障碍物和种子层的反应形成合金内衬用于互连应用
公开(公告)号：US20130000962A1
公开(公告)日：2013-01-03
申请号：US13614492
申请日：2012-09-13
申请人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami
发明人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami
IPC分类号： H05K1/09
CPC分类号： H01L21/76846 , H01L21/76844 , H01L21/76858 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.
摘要翻译：提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。

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