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31. 发明申请

US20120280397A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120280397A1
公开(公告)日：2012-11-08
申请号：US13463071
申请日：2012-05-03
申请人： Jung Geun KIM , Whee Won Cho , Eun Soo Kim
发明人： Jung Geun KIM , Whee Won Cho , Eun Soo Kim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76883 , H01L21/3215 , H01L21/76825
摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
摘要翻译：一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和在Cu层的表面上的金属元素。

32. 发明申请

US20080268608A1 METHOD OF FABRICATING A FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪速存储器件的方法
公开(公告)号：US20080268608A1
公开(公告)日：2008-10-30
申请号：US11951926
申请日：2007-12-06
申请人： Suk Joong Kim , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
发明人： Suk Joong Kim , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
IPC分类号： H01L21/76
CPC分类号： H01L27/11521
摘要： In a method of fabricating a flash memory device, after an isolation trench is formed, a bottom surface and sidewalls of the trench are gap-filled with a HARP film having a favorable step coverage. A wet etch process is performed such that the HARP film remains on the sidewalls of a tunnel dielectric layer, thereby forming a wing spacer. Accordingly, the tunnel dielectric layer can be protected and an interference phenomenon can be reduced because a control gate to be formed subsequently is located between floating gates.
摘要翻译：在制造闪速存储器件的方法中，在形成隔离沟槽之后，沟槽的底表面和侧壁间隙填充有具有良好阶梯覆盖率的HARP膜。执行湿蚀刻工艺，使得HARP膜保留在隧道介电层的侧壁上，从而形成翼间隔物。因此，由于随后要形成的控制栅极位于浮置栅极之间，所以可以保护隧道介质层并且可以减小干扰现象。

33. 发明授权

US07682900B2 Method of fabricating flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07682900B2
公开(公告)日：2010-03-23
申请号：US11964298
申请日：2007-12-26
申请人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
发明人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/11521
摘要： The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。根据该方法，在半导体衬底中形成选择晶体管和存储单元，并且形成结。选择晶体管和相邻存储单元之间的半导体衬底使用硬掩模图案过蚀刻。因此，可以禁止电子的迁移，并且可以提高程序干扰特性。此外，在存储单元之间形成空隙。因此，可以减少存储单元之间的干扰现象，因此可以提高闪存器件的可靠性。

34. 发明申请

US20090029522A1 Method of Forming Isolation Layer of Semiconductor Device 审中-公开
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090029522A1
公开(公告)日：2009-01-29
申请号：US11954470
申请日：2007-12-12
申请人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Jong Hye Cho
发明人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Jong Hye Cho
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L21/31116
摘要： A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.
摘要翻译：一种形成半导体器件的隔离层的方法，包括在半导体衬底上形成第一绝缘层，该半导体衬底包括在半导体衬底中形成的沟槽，用盐代替第一绝缘层的顶表面，除去盐以扩大第二绝缘层的侧壁之间的空间第一绝缘层，并且在第一绝缘层上形成第二绝缘层，使得沟槽间隙填充。因此，沟槽可以容易地用绝缘材料间隙填充。

35. 发明申请

US20070141842A1 Method of Manufacturing Semiconductor Device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070141842A1
公开(公告)日：2007-06-21
申请号：US11427559
申请日：2006-06-29
申请人： Whee Won Cho , Jung Kim , Sang Kim
发明人： Whee Won Cho , Jung Kim , Sang Kim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76829
摘要： Disclosed herein is a method of manufacturing a semiconductor device. The method includes forming an etch-stop film on a semiconductor substrate in which a predetermined structure is formed, and then forming an interlayer insulating film. The method also includes etching a predetermined region of the interlayer insulating film, and then stopping the etch process at the etch-stop film, to form a damascene pattern. The method employs an etch-stop film made of a material having a low dielectric constant. Accordingly, an increase in the capacitance due to an etch-stop film formed of the existing material having a high dielectric constant can be prevented. It is therefore possible to prevent a reduction of RC delay and also to accelerate the operating speed of devices.
摘要翻译：本文公开了一种制造半导体器件的方法。该方法包括在其中形成预定结构的半导体衬底上形成蚀刻停止膜，然后形成层间绝缘膜。该方法还包括蚀刻层间绝缘膜的预定区域，然后停止蚀刻停止膜处的蚀刻工艺以形成镶嵌图案。该方法采用由具有低介电常数的材料制成的蚀刻停止膜。因此，可以防止由具有高介电常数的现有材料形成的蚀刻停止膜引起的电容的增加。因此可以防止RC延迟的降低并且还可以加速设备的操作速度。

36. 发明申请

US20090170321A1 Method of Forming Isolation Layer of Semiconductor Memory Device 有权
标题翻译：形成半导体存储器件隔离层的方法
公开(公告)号：US20090170321A1
公开(公告)日：2009-07-02
申请号：US12137380
申请日：2008-06-11
申请人： Whee Won Cho , Jong Hye Cho
发明人： Whee Won Cho , Jong Hye Cho
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , H01L27/11521
摘要： A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.
摘要翻译：一种形成半导体存储器件的隔离层的方法。根据本发明的实施例，提供了形成有沟槽的半导体衬底。在包括沟槽的半导体衬底上形成第一电介质层。通过执行第一蚀刻工艺以去除第一介电层的一部分，随后进行退火处理来加宽沟槽的开口宽度。作为蚀刻和退火工艺的结果，在第一介电层中形成的含氟杂质通过执行第二蚀刻工艺而被除去。在包括第一介电层的半导体衬底之上形成第二电介质层。

37. 发明申请

US20080220605A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20080220605A1
公开(公告)日：2008-09-11
申请号：US11955836
申请日：2007-12-13
申请人： Jung Gu Lee , Whee Won Cho , Seong Hwan Myung , Suk Joong Kim
发明人： Jung Gu Lee , Whee Won Cho , Seong Hwan Myung , Suk Joong Kim
IPC分类号： H01L21/283
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention discloses a method of manufacturing a flash memory device comprising the steps of forming a first insulating layer and a first conductive layer on a semiconductor substrate; etching the first conductive layer, the first insulating layer and the semiconductor substrate to form a trench; forming an isolation layer on a region on which the trench is formed; forming a second conductive layer to make the second conductive layer contact with the first conductive layer; and removing the second conductive layer formed on the isolation layer.
摘要翻译：本发明公开了一种制造闪速存储器件的方法，包括以下步骤：在半导体衬底上形成第一绝缘层和第一导电层; 蚀刻第一导电层，第一绝缘层和半导体衬底以形成沟槽; 在形成有沟槽的区域上形成隔离层; 形成第二导电层以使第二导电层与第一导电层接触; 以及去除形成在隔离层上的第二导电层。

38. 发明申请

US20080224272A1 Active Structure of a Semiconductor Device 有权
标题翻译：半导体器件的有源结构
公开(公告)号：US20080224272A1
公开(公告)日：2008-09-18
申请号：US11771484
申请日：2007-06-29
申请人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
发明人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
IPC分类号： H01L29/06
CPC分类号： H01L21/76229 , H01L29/0657
摘要： An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.
摘要翻译：半导体器件的有源结构。一方面，半导体器件的有源结构包括第一至第（N）个第场区域，以及与第一至第（N + 1）个第一至第（n）个第场区域，其中第一至第（n + 1）个第个有源区域中的一个或多个在其边缘部分连接以封闭一个或多个的领域地区。另一方面，半导体器件的有源结构包括第一至第（n）场区域，以及与第一至（n）个有源区域连接到第（n + 2）个第和第（n + 3）个区域，在其边缘部分处有效区域，关闭场区域。

39. 发明授权

US08148267B2 Method of forming isolation layer of semiconductor memory device 有权
标题翻译：形成半导体存储器件隔离层的方法
公开(公告)号：US08148267B2
公开(公告)日：2012-04-03
申请号：US12137380
申请日：2008-06-11
申请人： Whee Won Cho , Jong Hye Cho
发明人： Whee Won Cho , Jong Hye Cho
IPC分类号： H01L21/302 , H01L21/461 , H01L21/311
CPC分类号： H01L21/76224 , H01L27/11521
摘要： A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.
摘要翻译：一种形成半导体存储器件的隔离层的方法。根据本发明的实施例，提供了形成有沟槽的半导体衬底。在包括沟槽的半导体衬底上形成第一电介质层。通过执行第一蚀刻工艺以去除第一介电层的一部分，随后进行退火处理来加宽沟槽的开口宽度。作为蚀刻和退火工艺的结果，在第一介电层中形成的含氟杂质通过执行第二蚀刻工艺而被除去。在包括第一介电层的半导体衬底之上形成第二电介质层。

40. 发明授权

US07652352B2 Active structure of a semiconductor device 有权
标题翻译：半导体器件的主动结构
公开(公告)号：US07652352B2
公开(公告)日：2010-01-26
申请号：US11771484
申请日：2007-06-29
申请人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
发明人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
IPC分类号： H01L29/06
CPC分类号： H01L21/76229 , H01L29/0657
摘要： An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.
摘要翻译：半导体器件的有源结构。一方面，半导体器件的有源结构包括与第一至第（n）场区域交替形成的第一至第（n）场区域和第一至第（n + 1）个有源区域，其中一个或多个第一至第（n + 1）个有源区域在其边缘部分连接以封闭一个或多个场区域。另一方面，半导体器件的有源结构包括与第一至第（n）场区域交替形成的第一至第（n）场区域和第一至第（n + 1）个有源区域，其中第一和第 n + 1）个有源区域在其边缘部分连接到第（n + 2）个和第（n + 3）个有效区域，关闭场区域。

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