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    • 31. 发明授权
    • Method for manufacturing a nonvolatile semiconductor memory device having increased hot electron injection efficiency
    • 制造具有增加的热电子注入效率的非易失性半导体存储器件的方法
    • US06303438B1
    • 2001-10-16
    • US09017216
    • 1998-02-02
    • Atsushi HoriJunichi KatoShinji OdanakaSeiki Ogura
    • Atsushi HoriJunichi KatoShinji OdanakaSeiki Ogura
    • H01L21336
    • H01L29/66825H01L21/28273H01L29/42336H01L29/7885
    • The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate which is capacitively coupled to the floating gate via a second insulating film. The first insulating film includes a first gate insulating film portion formed in the first surface region, and, a second gate insulating film portion formed in the step side region and the second surface region. The control gate is formed on the first gate insulating film portion. A part of the floating gate faces the step side region via the second gate insulating film portion, and another part of the floating gate is adjacent to the control gate via the second insulating film.
    • 本发明的非易失性半导体存储器件包括:半导体衬底,具有包括第一层的第一表面区域,低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域,其形成在半导体衬底的表面中,以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及通过第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一绝缘膜包括形成在第一表面区域中的第一栅极绝缘膜部分和形成在台阶侧区域和第二表面区域中的第二栅极绝缘膜部分。 控制栅极形成在第一栅极绝缘膜部分上。 浮栅的一部分经由第二栅极绝缘膜部分面对台阶侧区域,浮栅的另一部分经由第二绝缘膜与控制栅极相邻。
    • 32. 发明授权
    • Nonvolatile semiconductor memory device and method for fabricating the
same and semiconductor integrated circuit
    • 非易失性半导体存储器件及其制造方法和半导体集成电路
    • US6121655A
    • 2000-09-19
    • US848
    • 1997-12-30
    • Shinji OdanakaKaori AkamatsuJunichi KatoAtsushi HoriSeiki Ogura
    • Shinji OdanakaKaori AkamatsuJunichi KatoAtsushi HoriSeiki Ogura
    • G11C16/04H01L21/336H01L21/8247H01L27/115H01L29/423H01L29/788H01L29/792H01L29/76
    • H01L29/66825H01L29/42324H01L29/7885
    • The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.
    • 本发明的非易失性半导体存储器件包括:半导体衬底,具有包括第一层的第一表面区域,低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域,其形成在半导体衬底的表面中,以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层, 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。
    • 37. 发明授权
    • Dielectric ceramic composition
    • 介电陶瓷组合物
    • US5153154A
    • 1992-10-06
    • US724884
    • 1991-07-02
    • Junichi KatoHiroshi Kagata
    • Junichi KatoHiroshi Kagata
    • C01G33/00C04B35/497
    • C04B35/497C01G33/006C01P2006/40C01P2006/80
    • A dielectric ceramic composition possessing a high relative dielectric constant, a high unloaded Q value, and an excellent temperature characteristic is expressed as xPbO-.sub.y (Mg.sub.1/3 Nb.sub.2/3)O.sub.2 -zCaO, where x+y+z=1, and x, y, z are in the following ranges, 0.05.ltoreq.x.ltoreq.0.45, 0.4.ltoreq.y.ltoreq.0.55, 0.15.ltoreq.z.ltoreq.0.4, or expressed as xPbO-y(Ni.sub.1/3 Nb.sub.2/3) O.sub.2 -zCaO, where x+y+z=1, and x,y, z are in a quadrangular region with vertexes at A (x=0.25 y=0.7 z=0.05), B (x=0.2 y=0.7 z=0.1), C (x=0.2 y=0.45 z=0.35), and D (x=0.35 y=0.45 z=0.2), which are composition points of a ternary system with vertexes at PbO, (Ni.sub.1/3 Nb.sub.2/3)O.sub.2, and CaO.
    • 具有高相对介电常数,高无载Q值和优异温度特性的介电陶瓷组合物表示为xPbO-y(Mg1 / 3Nb2 / 3)O2-zCaO,其中x + y + z = 1,x ,y,z在以下范围内,0.05≤x≤0.45,0.4≤y≤0.55,0.15≤z≤0.4,或表示为xPbO-y(Ni1 / 3Nb2 / 3)O2-zCaO,其中x + y + z = 1,x,y,z处于A(x = 0.25y = 0.7z = 0.05)的顶点的四边形区域,B(x = 0.2 y = 0.7 z = 0.1),C(x = 0.2 y = 0.45 z = 0.35)和D(x = 0.35 y = 0.45 z = 0.2),它们是具有PbO顶点的三元体系的组成点(Ni1 / 3Nb2 / 3)O2和CaO。
    • 39. 发明授权
    • Multi-layer ceramic capacitor
    • 多层陶瓷电容
    • US4752858A
    • 1988-06-21
    • US24778
    • 1987-03-11
    • Yoichiro YokotaniJunichi KatoToshihiro Mihara
    • Yoichiro YokotaniJunichi KatoToshihiro Mihara
    • H01G4/30C04B35/499H01G4/12H01B3/12H01G4/10
    • C04B35/499H01G4/1209
    • Material forming dielectric ceramics includes an oxide containing a component A and a component B. The component A is selected from a group I of lead, calcium, strontium, and barium. The component B is selected from a group II of magnesium, nickel, titanium, zinc, niobium, and tungsten. The component A includes lead and at least one of the other substances in the group I. The component B includes at least two of the substances in the group II. A ratio between values a and b is chosen so that a/b>1.00, where the value a denotes a total mol value of the substances in the component A and the value b denotes a total mol value of the substances in the component B. Electrode layers are made of copper or an alloy principally containing copper. Since the firing temperature of the dielectric ceramics is low, excellent characteristics of a capacitor are enabled in spite of the fact that electrodes contain copper.
    • 材料形成介电陶瓷包括含有组分A和组分B的氧化物。组分A选自铅,钙,锶和钡的组I。 组分B选自镁,镍,钛,锌,铌和钨的组II。 组分A包括铅和组I中的至少一种其它物质。组分B包括组II中的至少两种物质。 选择值a和b之间的比率使得a / b> 1.00,其中a表示组分A中物质的总摩尔值,值b表示组分B中物质的总摩尔值。 电极层由铜或主要含有铜的合金制成。 由于电介质陶瓷的烧制温度低,所以尽管电极含有铜,但电容器的特性也是优异的。