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31. 发明授权

US07485536B2 Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
标题翻译：通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成
公开(公告)号：US07485536B2
公开(公告)日：2009-02-03
申请号：US11326178
申请日：2005-12-30
申请人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
发明人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
摘要翻译：一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。

32. 发明申请

US20100200917A1 NONPLANAR DEVICE WITH STRESS INCORPORATION LAYER AND METHOD OF FABRICATION 有权
标题翻译：具有应力合并层的非平面装置和制造方法
公开(公告)号：US20100200917A1
公开(公告)日：2010-08-12
申请号：US12767681
申请日：2010-04-26
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
摘要翻译：包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

33. 发明授权

US06909151B2 Nonplanar device with stress incorporation layer and method of fabrication 有权
标题翻译：具有应力结合层的非平面器件及其制造方法
公开(公告)号：US06909151B2
公开(公告)日：2005-06-21
申请号：US10607632
申请日：2003-06-27
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
摘要翻译：包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

34. 发明授权

US07714397B2 Tri-gate transistor device with stress incorporation layer and method of fabrication 有权
标题翻译：具有应力结合层的三栅晶体管器件及其制造方法
公开(公告)号：US07714397B2
公开(公告)日：2010-05-11
申请号：US11493789
申请日：2006-07-25
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
摘要翻译：包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

35. 发明授权

US07241653B2 Nonplanar device with stress incorporation layer and method of fabrication 有权
标题翻译：具有应力结合层的非平面器件及其制造方法
公开(公告)号：US07241653B2
公开(公告)日：2007-07-10
申请号：US11173443
申请日：2005-06-30
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
摘要翻译：包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

36. 发明授权

US08405164B2 Tri-gate transistor device with stress incorporation layer and method of fabrication 有权
标题翻译：具有应力结合层的三栅晶体管器件及其制造方法
公开(公告)号：US08405164B2
公开(公告)日：2013-03-26
申请号：US12767681
申请日：2010-04-26
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
摘要翻译：包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

37. 发明申请

US20140103396A1 STRAIN-INDUCING SEMICONDUCTOR REGIONS 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US20140103396A1
公开(公告)日：2014-04-17
申请号：US14133457
申请日：2013-12-18
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/10 , H01L29/78
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

38. 发明授权

US08530884B2 Strain inducing semiconductor regions 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US08530884B2
公开(公告)日：2013-09-10
申请号：US13160886
申请日：2011-06-15
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/06 , H01L31/072
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

39. 发明申请

US20120061649A1 STRAIN-INDUCING SEMICONDUCTOR REGIONS 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US20120061649A1
公开(公告)日：2012-03-15
申请号：US13160886
申请日：2011-06-15
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

40. 发明授权

US07825400B2 Strain-inducing semiconductor regions 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US07825400B2
公开(公告)日：2010-11-02
申请号：US11450745
申请日：2006-06-09
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

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